27

DESIGN

TECHNIQUES FOR

LOW NOISE CMOS OPERATIONAL AMPLIFIERS

Hans W. Klein *X and Walter L.

Engl

*2

ABSTRACT A comparison of three different approaches on the reduction of low frequency noise in single ended CMOS operational amplifiers is made. The particular concepts are the increase of the gare areas, the chopper tech nique, and the Auto-Zero technique, respectively. Measured data from re alized circuits as well as predicted data derived from equations are pre
sented.

I. INTRODUCTION Recent CMOS process developments have primarily led to complex high speed digital circuits. Currently, analog circuits seem to be unable keeping pace with the performance of digital developments. One of the responsible factors limiting analog perfomance is the poor noise behav iour of the operational amplifiers (opamps). Three different approaches to the improvement of low frequency noise, also known as flicker noise (FN), will be discussed.

II. THE CLASSICAL APPROACH The enlargement of the gate area is the classical way of noise re duction. Many authors already stated that the low frequency noise power 2 of an MOS transistor is inversely proportional to the gate area e

e~2 n
where for a
a

.?W

La

width

length

(1)

characteristical parameter and a=l. But, in fact, also a=0.5 PolySi-CMOS process has been found empirically, that means, the actual geometry relationship depends on the particular process and, con sequently, has to be proved for each different process. However, larger gate areas perform less noise generation. Usually, the input stage of a multi-stage opamp limits the dynamic range of the total amplifier (supposed the input stage has a sufficient gain, e.g. >10). For this problem an extended strategy regarding the optimization of the noise-area-product wil 1 be presented. The white noise (WN) as well as the FN regions are considered and the results are dis cussed based on measurements of realized opamps. Basically, the optimi zation method prescribes geometry ratios of the input stage devices, such that all noise sources contribute the same part to the total noise. Now the gate areas can be magnified until the particular noise requirements are fulfilled. With respect to (1), and especially for a<l, this is most effectively done by increasing the width of the input stage devices. However, to reduce a certain noise level (increase dynamic range) by 6 dB the input stage area has to be enlarged approximately four times.
is
a

*1) *2)

Institut fuer Mikroelektronik Stuttgart, Allmandring 30a, D-7000 STUTTGART 80, West-Germany Institut fuer Theoretische Elektrotechnik, Univ. of Aachen, Kopernikusstr. 16, D-5100 AACHEN, West-Germany

28

It should be noted that either the FN or the WN range can be opti mized with respect to chip area, which will be discussed in detail at the conference. Another problem of the classical method relates to the effects on specs like gain a or unity gain frequency f (gain bandwidth product). As it will be shown, a noise reduction not influencing these and other specs is impossible. This causes many problems during the desiqn phase. In addition, very large circuit layouts result for low noise opamps which seems to be the improper direction regarding VLSI trends. III. THE CHOPPER TECHNIQUE The basic idea is to transform the input signal spectrum by a first chopper (rectangular modulator) into a frequency range where the opamp generates less noise. Afterwards, the amplified signal is recovered by a second chopper. This technique has already been used for an NMOS appli cation by Hsieh and Gray /2/ where fully differential opamps have been used. Another approach is shown in fig.la and lb. Both circuits have the typical differential-in-single-out configuration which only requires 50% of chip area with respect to the differential concept (50% of external components, no external common-mode control, etc.). The circuit in fig.lb is very interesting, since the second chopper has been merged with the current mirror (M3, M4) and, hence, chip area is further reduced 13/. Fig.2 shows the noise performance of both circuits (choppers ON and OFF), and in table I some characteristical data of realized circuits are listed. At a bandwidth of 1 Hz a dynamic range of approx. 145 dB has been achieved. Another important fact is the complete opamp can be designed like a static one in spite of the presence of choppers. A drawback of this approach is that there exists a certain ripple on the output signal at the chopper frequency which must not be aliased into the baseband by subsequent sampling or chopping stages. In addition, the clock feedthrough always introduces some static (and dynamic) errors and the offset of the 2nd stage still remains. The resulting offset voltage can exceed that one of the unchopped counterpart, but, normally, it is in the same order of magnitude.

IV. THE AUTO-ZERO TECHNIQUE There are several ways of performing an Auto-Zero opamp (AZO) which actually depend on the environment the opamp operates in. A stand-alone as well as a dedicated AZO concept for switched-capacitor (SC) circuits will be discussed. However, the basic idea is always the same: an ampli fier is switched into a feedback (nulling) loop where a correction volt age is applied to an appropriate node so that the actual offset (wherev er it stems from) is compensated. The evaluation of the basic effects of a general AZ-circuit delivers that, for instance, the DC offset is re duced by the gain of the main amplifier (e.g., >60 dB) resulting in a drastical offset improvement. In addition, not only DC errors but also low frequency noise is reduced. If, for a first impression, the time for the nulling sequence is neglected the analysis for the FN improvement factor IF delivers the theoretical limit as 1.3 f U /fA7 AZ IF (2)
=

where f and f-j denote the upper and lower border of the considered fre quency spectrum, and f.7 is the Auto-Zero-frequency, respectively. As an example, the maximum improvement of the dynamic range by an AZO for the

/My^)

29

PCM frequency band (0.3-3.4 kHz) is about 35 dB which j s a considerable value. Additionally, this AZ concept is suited to reduce all actual low frequency errors wherever they stem from. For instance, the power supply rejection is improved as well, the corresponding equations will be dis cussed.
V. SUMMARY Three different approaches for the reduction of low frequency noise in single-ended CMOS opamps are compared. The classical large area con cept has disadvantages like high cost (large chip area) and lower degrees of design freedom, since noise optimization cannot be achieved independ ently from other specs. For low noise applications this approach rather quickly reaches practical limitations. The chopper technique exhibits ex cellent noise performance but introduces some high frequency noise and in most cases additional DC offset due to the choppers themselves. On the other hand, small sized input stage devices can be used Therefore, low noise chopper opamps can be realized with less area need than their clas sical counterparts which is rather on the track of VLSI trends The AZO's exhibit the best DC-offset, FN, and PSRR performance. In best cases they are as small as chopper opamps (e.g., in SC-filters) and, hence, VLSI suited, too. Additionally, AZO's are most attractive to low frequency ap plications since the improvement increases with the increasing ratio of Auto-Zero to signal frequency

The authors wish to thank R. Brock for fabricating the CMOS ooamps and for the design of different chopper amplifiers G.

Acknowledgement

Teepe*^

/I/ Ill 13/

REFERENCES J.C. Bertrails, "Low-Frequency Noise Considerations for MOS Amplifier Design", IEEE JSSC, SC-14, Auq. 1979. K.C. Hsieh and P R Gray, "A Low-Noise Chopper-Stabilized Differential Switched-Capacitor Filtering Technique", IEEE Digest ISSCC, Feb. 1981. H.W. Klein, "Design and Optimization of CMOS Operational Amplifiers Switched-Capacitor Applications", Ph D Thesis (in German), University of Aachen, West-Germany, 1983

specs
o

fig.la
85 f 780
a

circuit

fig.lb

remarks

^M_
e p.

en ]ao
60 800 0.5

pt0tal
size

80 280 37 250 55 600 0.36

dB kHz

deg

C. =36
<a

nV/-/Hz,
dto
mm
,
,

pF
1

kHz, chopper OFF

chopper ON

uW +/- 5 V

Al-gate CMOS
chopper opamps

TABLE I: Measured characteristics of

30

i.
20dB-in

>

(|m.p-ftu
M2} 1-f.J4
Ml

VDD

i* HH

MB
OUT

M3j.|.Tm4

VDD

s
Fig. la,b:

IN IN

7p.L.li"9
4-*

V
IN IN

M2

^s

M6
OUT

vss

<
*..

vss

Two

examples

of

diff-in-single-out chopper opamps

vWfiz
-110-16

-1201
-130

Chopper
-K(H
.X-JU.j-1
--1-r-

OFF
ON

rrT

Sfciur^O-0-^10k f/Hz

10

100

1k

Fig.

2: Noise

performance

of circuits

in

fig. la (x) and fig. lb (o)

'HI

Fig.

3: A

general

Auto-Zero realization