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An Efcient SoC Test Technique by Reusing On/Off-Chip Bus Bridge

Jaehoon Song, Student Member, IEEE, Hyunbean Yi, Member, IEEE, Juhee Han, and Sungju Park, Member, IEEE
AbstractTodays system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efciently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efcient functional and structural testing. The testing time can be signicantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges. Index TermsAdvanced microcontroller bus architecture (AMBA), bus bridge, peripheral component interconnect (PCI), system-on-a-chip (SoC), test time, testability.

I. INTRODUCTION

S deep-submicrometer techniques are increasingly developed, it is possible to design and manufacture a system-on-a-chip (SoC) comprised of various intellectual-property (IP) cores meeting short time-to-market requirements. Although the design time can be reduced by utilizing reusable IP cores, the testing time is signicantly increased because of the high complexity of the SoC. The testing cost is mainly affected by the memory size and application time of the automatic test equipment (ATE), the structure of the core test wrapper, the test-access mechanism (TAM), test power, and test methodology [1][4]. Improving test quality while keeping testing costs low becomes crucial to survive in the emerging silicon market. To minimize silicon overhead induced by the design-for-testability (DFT), it becomes highly benecial to reuse on-chip functional blocks as fully as possible to achieve minimal test time [5][8].

Manuscript received January 03, 2008; revised May 04, 2008. First published August 04, 2008; current version published March 11, 2009. This work was supported in part by the System IC 2010 Project of the Consortium of Semiconductor Advanced Research (COSAR) in Korea. The earlier version of this paper was presented at the Asian Test Symposium 2007. This paper was recommended by Associate Editor V. De. J. Song and S. Park are with the Department of Computer Science and Engineering, Hanyang University, Kyeonggi-do 425-791, Korea (e-mail: jhsong@mslab.hanyang.ac.kr; parksj@mslab.hanyang.ac.kr). H. Yi is with the Department of Electrical and Computer Engineering, University of Massachusetts at Amherst, Amherst, MA 01002 USA (e-mail: bean@engin.umass.edu). J. Han is with SAMSUNG Electronics, Yongin-si 446-711, Korea (e-mail: jh0706.han@samsung.com). Digital Object Identier 10.1109/TCSI.2008.2002550

Advanced microcontroller bus architecture (AMBA) is an on-chip bus architecture that is used to strengthen the reusability of IP cores, and the AMBA advanced high-performance bus (AHB) is often used as the backbone bus of a high-performance SoC [9]. To test embedded cores in such an AMBA-based SoC, test interface controller (TIC), external bus interface (EBI), and test wrappers are extensively adopted [9][13]. The TIC [9] is for the testing of an AMBA-based system, performing basic read/write transactions as an AMBA bus master. The EBI is used as an external test bus (TBUS) to transfer test data. The test wrapper allows access to the inputs and outputs of an embedded core that are not directly connected to the on-chip bus. However, the TIC [9] uses a single path between the TBUS and the AHB to transfer the address and test data into the embedded cores and to transfer the test responses through the TBUS. Therefore, write and read data transactions must be performed exclusively with additional turnaround cycles to avoid the bus conict on the TBUS. This leads to an increased amount of testing time for not only functional but also structural scan tests. In [10], scan test wrappers are designed for each core, but the scan-in and scan-out must be performed exclusively, resulting in an extensive number of test cycles. In [11], although scan chains are scanned in and out concurrently, the modication to the AHBAPB bridge logic impairs compatibility with the AMBA system. While preserving complete compatibility with AMBA protocols, simultaneous scan shifting in and out is supported in [13]; however, in the functional test mode, testing time can be considerably increased due to the inherent TIC characteristics. The peripheral-component-interconnect (PCI) bus has been widely implemented to connect chips and adaptors on a board [14]. For a PCI board that has SoCs embedded with an AMBA internal bus, the AHB-PCI bus bridge, often referred to as an on/off-chip bus bridge, is a necessary component to connect the on-chip bus with the off-chip bus. Such system chips with the AHB-PCI bus bridge have been widely adopted for various applications such as sound, graphic, and network cards [15][17]. In this paper, an efcient TAM is proposed to reuse a functional on/off-chip bus bridge as a test interface. A case for on-chip AHB and off-chip PCI is extensively studied to evaluate the efciency of the proposed method. The test application time is considerably reduced by providing the dedicated test-stimulus-input and the test-response-output paths and by excluding the bus-direction turnaround delays. This technique maximally reuses the on/off-chip bus bridge to transfer the external test data from an ATE into a SoC; thereby, the silicon overhead for the test-interface logic is minimized.

1549-8328/$25.00 2009 IEEE

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Fig. 1. Example of AMBA system with the TIC.

This paper is organized as follows. Conventional TAMs for AMBA-based SoCs are introduced in Section II, and our proposed technique is described in Section III. In Section IV, design experiments show the superiority of this technique in both the area and test-application times. Section V presents the conclusion. II. TEST INTERFACES FOR AMBA-BASED SOC A conventional AMBA-based system is comprised of AHB and advanced peripheral bus (APB) as shown in Fig. 1. The AHB and APB have separate read and write data buses for on-chip transactions [9]. The AHB interfaces high-speed cores such as a microprocessor, and the APB is used to interface any peripherals which have low bandwidth and do not require the high performance of a pipelined bus interface [9]. An AHBAPB bridge must be adopted to adjust different speeds and protocols of the AHB and APB. The TIC IP core shown in Fig. 1 is a TIC for the AMBA-based system that performs basic read/write transactions as an AMBA bus master [9]. In order to access the external memory modules outside an AMBA-based SoC, unidirectional 32-bit address and bidirectional 32-bit data pins of the EBI are generally used [18][21]. By utilizing the functional buses of the EBI and AMBA as test buses, an additional TAM is not required. In the test mode, for the isolation, controllability, and observability of the target core, the test wrapper (also called a test harness) is dened as shown in Fig. 2. The test wrapper is congured according to the input/output and test strategy of each core. Even cores that do not comply with the AMBA can be accessed through this wrapper [9]. To improve test quality, it is needed to perform both functional and structural tests. In functional tests, all of the TICbased techniques require additional delays for the bus-direction turnaround to avoid bus conict for read/write transfers on the same test bus, TBUS as shown in Fig. 1. For structural tests, scan test harness with a number of temporary registers is proposed in [10] in order to support cores with more scan chains and I/Os than the bus width. However, the scan data cannot be

Fig. 2. Test wrapper.

shifted in and out simultaneously, leading to a lengthy test-application time. In [11], concurrent scan shift in and out became possible by taking part of the EBI address bus as the scan-out paths. However, the AHBAPB bridge has to be modied, impairing the compatibility with AMBA in test mode, so functional testing becomes impossible. In [13], a design scheme is introduced to provide concurrent scan shifting in and out as well as conventional functional testing, while preserving complete compatibility with the AMBA protocols. However, because the TIC used requires the same TBUS for both read and write transactions, additional turnaround cycles are needed to change bus direction, signicantly increasing the functional testing time. The on/off-chip bus bridge shown in Fig. 1 is a necessary component to connect the SoC with an off-chip bus. This paper introduces a new design technique for the AMBA-based SoC in order to signicantly reduce test-application time by reusing the design resource of the on/off-chip bus bridge as a test interface. III. PROPOSED TAM FOR AMBA-BASED SOC The main contribution of our technique is to reuse the on/offchip bus bridge as a test interface during the test mode. The AHB master component on the bridge is reused as an interface between the ATE and the chip under test, and then, the ATE acts as a virtual bus master. By utilizing the functional buses as dedicated test paths and eliminating the bus-direction turnaround delays, testing time is considerably reduced in both functional

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Fig. 3. Proposed test-access architecture.

and structural tests. Compatibility with the AMBA protocol is maintained without the need for any internal modication of the reusable cores and functional bus structure. In this paper, the bridge with the test controllability is referred to as a test-ready bridge (TR-bridge for short). A. Proposed Test-Access Architecture Fig. 3 shows the proposed test-access architecture in SoC level. The TR-bridge allows externally applied test stimuli to be converted for internal bus transfers. The bridge provides both functional- and structural-test modes. Functional tests reuse the test data that were used for design verication. The TR-bridge uses handshake signals of test request (TREQ), test acknowledgement (TACK), and command byte enable (CBE) to control the application of test vectors. The CBE signals are used for test-mode control as well as for the PCI functional interface [14]. During the functional- or structural-test mode, the AD bus of the PCI interface and EBIDATABUS of the EBI shown in Fig. 3 are dedicated to apply the test stimuli and to output the test responses, respectively. The EBI is generally used to communicate with tightly coupled off-chip memories during normal system operation. The TestRead signal from the TR-bridge to the EBI changes the direction of the EBIDATABUS to output the test response. The ScanTestMode signal enables test wrappers for structural scan testing. B. On/Off-Chip Bus Bridge With Test Controllability This section describes the proposed AHB-PCI bus bridge with test controllability, and Fig. 4 shows the architecture of the bridge. The bridge mainly consists of AHB-master, PCI-target, AHB-slave, PCI-initiator, and test-controller blocks. During normal system operation, the AHB-master and PCI-target

blocks act as an AHB bus master and a PCI bus slave, respectively. These components operate when the SoC becomes a slave with regard to the PCI bus. The AHB-slave and PCI-initiator blocks act as an AHB bus slave and a PCI bus master, respectively. These components operate when the SoC is a bus master with regard to the PCI bus during normal system operation. In Fig. 4, the shaded area designated as the hybrid TIC (HTIC) is the test-control logic, which is disabled during normal system operation by deasserting the TREQ signal. Generally, the bridge structure of Fig. 4 excluding the HTIC block is common to the on/off-chip bus bridges targeting other bus interfaces. Fig. 5 shows the TR-bridge acting as a TIC in which only the HTIC and AHB-master blocks are active during test mode. The HTIC, which consists of a multiplexer and a simple test-controller block, is a key test-control block that interfaces an ATE to the AHB-master block. The multiplexer controls the data path to the AHB-master block. In test mode, the AD bus of the PCI interface is directly connected to the AHB-master block and is not connected via the PCI target and PCI Write FIFO blocks. Therefore, during the test mode, there is no need to be compatible with the complex PCI protocol. This scheme simplies the test sequences and is not limited by the PCI speed limit (33 or 66 MHz), which is much lower than the AHB. The AHB bus master block, which is a system functional block, is reused during the test mode to allow externally applied test vectors on the AD bus to be transferred into the internal AHB bus, keeping the compatibility with the AHB protocol. The external test-control interface consists of a test clock (TCLK), two control signals dedicated to the test mode (TREQ, TACK), and control signals shared by the PCI interface (CBE[2:0]). Tables I and II describe the operation of the external test-control interface signals of the HTIC. The signals have different

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Fig. 4. AHB-PCI bus bridge with test controllability during normal system operation.

Fig. 5. AHB-PCI bus bridge with test controllability during test mode.

functions, depending on the mode in operation. The dedicated device pins TREQ and TACK indicate the test-bus request and test-bus acknowledge, respectively. TACK gives an external indication that the test bus has been granted and also indicates when a test access has been completed. When TACK is low,

the current test vector must be extended until TACK becomes high. The CBE[2:0] signals are only sampled by the HTIC when TACK is high. There are four different types of test vectors associated with the test interface, which are address, write, read, and control

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TABLE I TEST-CONTROL SIGNALS DURING NORMAL SYSTEM OPERATION

TABLE II TEST-CONTROL SIGNALS DURING EITHER FUNCTIONAL- OR STRUCTURAL-TEST MODE

vectors. During the test mode, the CBE[1:0] signals describe the type of test vector to be applied in the following cycle, while the CBE [2] differentiates the functional- and structural-test modes. An address vector is used to select a core to be tested. A write vector is for either functional- or structural-test stimulus, and a read vector is for the test responses. A control vector updates the control values of the AHB control signals such as HSIZE, HPROT, HTRANS, and HLOCK [9]. Therefore, the combinations of the test-control pins shown in Tables I and II cover all of the test-control cases of the TIC [9] and provide the additional structural-test mode. In general, test patterns are applied to the circuit under test through an ATE. Hence, the test data and control sequence for a conventional AMBA-based SoC embedding the TIC can be simply converted to the test sequence for a SoC with our TR AHB-PCI bridge. In order to efciently transfer the test vectors to and from a SoC externally, AD[31:0] of the PCI interface and EBIDATABUS[31:0] are reused as the external 32-bit test bus. The AD[31:0] bus, which transfers both the address and data in the normal mode, is adopted as a dedicated test input in the test mode. The EBIDATABUS[31:0] bus, which interfaces the external devices of a SoC during normal system operation, is connected to an ATE as the test-response output port during the test mode. Such test buses dedicated to write and read explicitly can reduce the test-application time signicantly, by not requesting a turnaround period to change a bus direction and by allowing simultaneous scan in and out operations. C. Operation of the TR-Bridge The state diagram shown in Fig. 6 illustrates the operation of the TR-bridge. The TACK signal is used to control all of the transactions around the state machine, except for the transition

Fig. 6. State diagram of the proposed HTIC.

from IDLE to START. With the assertion of TREQ and high response of TACK, the HTIC is entered into the test mode. The START state is used to prevent read and write vectors from entering before the address is initialized. This ensures that the rst vector applied is an address vector, so the START state is only exited when CBE[1:0] indicates an address vector. The state machine then moves to ADDRVEC, WRITEVEC, READVEC, and CONTVEC states according to values of the CBE[1:0]. Fig. 7 shows the TIC state diagram in [9]. In the TIC-based approach, a read vector or burst of read vectors is always followed by two additional vectors, LASTREAD and TURNAROUND, for the turnaround time of the test bus-direction change, as shown in Fig. 7. This is because the TIC-based scheme uses the same test bus interface external to the SoC for any type of transfer. Therefore, additional cycles are necessary to prevent the bus clash when the drivers of the test bus are changed [9]. This can signicantly increase the functional test time, because, in a real system, read transactions occur more frequently than the others. However, due to separate read and write test-bus interfaces, such turnaround states are not required in the proposed technique. As shown in Fig. 6, four states (ADDRVEC, WRITEVEC, READVEC, and CONTVEC) constitute a complete directed graph. Thus, any transition among these states needs only one clock cycle. For example, a control vector with the TIC-based approach always requires at least one address vector prior to the control vector [9]. However,

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From cases 1), 2), and 3), the total test-application times for the TIC-based and the proposed HTIC-based techniques can be, respectively, estimated as

(1) (2) Thus, the TIC-based scheme requires about three times more clock cycles than the proposed approach, as described in (3) Due to frequent changes of transaction types such as reading, writing, and addressing, the functional testing time is affected signicantly more than the structural-scan-testing time by (3). Figs. 8 and 9 show timing diagrams for the execution of an example sequence of events in both the proposed technique and the TIC-based scheme, respectively. The sequence used is as follows: Address . In Fig. 8, the CBE indicates what types of tests and vectors are applied in the following cycle. Initially, the CBE is used to apply an address vector followed by a read transfer. The HTIC samples the address vector, Addr A, after the T2 cycle. Then, the appropriate transfer on the AHB is initiated by reusing the AHB-master block on the TR-bridge. In the following cycle, the read vector, Read 1, is driven on to the EBIDATABUS from the AHB HRDATA on-chip bus and, then, sampled by the external test equipment. If the internal transfer cannot be completed, the TACK signal is driven to low, requiring another cycle such as at T5. In Fig. 8, after the burst of read transfers, a new address vector, Addr B, is applied. In the following cycle, the write data, Write1, are driven onto the AD bus and then driven onto the internal AHB bus. In Fig. 9, before the rst read cycle, the TBUS used to transfer the test vector must be in a state of high impedance, because the read-vector cycle is performed in opposite bus direction to the previous address-vector cycle. At the end of a burst of reads, the TIC must turn off the internal buffers for bus turnaround. Therefore, Figs. 8 and 9 show that two additional cycles are needed for a read transfer when using the techniques based on the TIC [9]. If all other transactions are considered, signicant reduction in the number of test cycles can be achieved. D. Structural-Test Interface For structural scan test of embedded cores, test wrappers are commonly used [22]. We adopt the technique in [13] for the AMBA-specic scan test wrappers (harnesses), which optimally utilize AMBA bus for the test-vector application and response observation. We also adopt the AHBAPB bridge bypass multiplexer in [13], which is used to speedup the structural test of embedded cores on the slow APB bus. However, the ad hoc logic for the dedicated scan-out path which uses the EBI address bus is excluded in our scheme. The scan-in and scan-out paths are used exclusively by the AD bus of the TR-bridge and the EBI data bus, respectively. Thus, concurrent scan-in and scan-out operations are possible

Fig. 7. State diagram of the TIC [5].

in our technique, the control vector can be applied independently by introducing the CONTVEC state, as shown in Fig. 6. This leads to a further reduction in the test-application time. In order to compare the TCLK cycles required by the proposed method and the TIC-based scheme, the number of transitions in the state diagrams is estimated for a series of test sequences. If , , , and number of state transitions are needed in Fig. 6, how many transitions are needed in Fig. 7? Three key cases are analyzed as follows: Case 1) The transition from READVEC to WRITEVEC or from READVEC to ADDRVEC requires three clocks as shown in Fig. 7 instead of one clock in the proposed method shown in Fig. 6. Thus, the TIC-based scheme takes clock cycles, whereas the proposed method just takes clock cycles. Case 2) The transition from READVEC to CONTVEC as shown in Fig. 6 requires one clock, but the same transition requires at least four clocks as shown in Fig. 7 because the last of more than one successive address vectors is considered as a control vector [9]. Therefore, the TIC-based scheme takes clock cycles, whereas the proposed method takes clock cycles. Case 3) The transition from WRITEVEC to CONTVEC as shown in Fig. 6 requires one clock, but the same transition requires at least two clocks as shown in Fig. 7 for the same reasons described in case 2). Therefore, the TICbased scheme takes clock cycles, whereas the proposed method takes clock cycles.

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Fig. 8. Timing diagram for the proposed TR-bridge scheme.

without requesting any read transactions of the AMBA bus during the scan shifting. Since our technique uses only the write transactions of the AMBA bus for scan testing (excluding the additional cycles for the read transactions), the scan test time can be further reduced. E. Integrity Test of the TR-Bridge In order to test the proposed TR-bridge shown as shaded in Fig. 10, scan chains and test wrappers are implemented to the bridge excluding the AHB-master and HTIC blocks, and they can be veried through embedded-core testing by simply applying functional verication sequences for the HTIC, including the patterns for Tables I and II. The self-test scheme for the TR-bridge on the AHB bus is shown in Fig. 11. The test sequence for the TR-bridge is summarized as follows. First, the address vector from the ATE is applied through the AD bus and AHB-master side with the HTIC. Then, the target scan chains or primary inputs (PIs) on the AHBslave side of the bridge are selected by the test wrapper. The scan-in or PI data are written to the circuit under test through path. Then, the target primary outputs the (POs) and scan chains are selected, and their values, including captured responses, are observed through the path. F. Operation of Structural Test Fig. 12 shows a timing diagram of the structural scan test for a simple core-under-test (CUT) with a single scan chain of length four, which is adopted to show the precise simulation steps. The structural-test mode is requested when the CBE [2] signal is high. During the structural-test mode, the ScanTestMode signal from the TR-bridge is asserted to enable the wrappers and AHBAPB bypass multiplexer. The scan in and

out paths are used exclusively by the AD bus of the TR-bridge and the EBI data bus, and then, concurrent test application and response observation are possible without requesting any read transaction to the AMBA bus during scan shifting. The key signals that pertain to the transfer of the test data and results are AD, HWDATA, HRDATA, and EBIDATABUS. The TREQ, CBE, and TACK are signals of the TR-bridge, which globally controls test operations. The CBE[1:0] indicates the type of content on either the AD or EBIDATABUS for the following cycle. The operation sequences are as follows. First, the address through the AD bus selects the target scan chains or PIs. The scan-in or PI data is then written to the CUT through the path. Next, the POs are selected and their values are observed through the path, followed by the capture operation performed by the ClockGenerator. Finally, scan chains are selected to shift out captured responses through the same path, while a scan-in operation is performed simultaneously through the dedicated scan-in and scan-out paths. Therefore, the proposed technique uses only write transactions to the AMBA bus during the scan test, causing no additional cycles for read transactions. G. Estimation of the Structural Test-Application Time To analytically compare the structural-scan test-application times between the exclusive scan-in/out method [10] and our current scheme, mathematical formulas are described in Sections III-G1 and 2. 1) Test-Application Time for Exclusive Scan In and Out Techniques: The test time for one test pattern for the exclusive scan in and out methods [3] can be calculated by

(4)

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Fig. 9. Timing diagram for the TIC-based scheme [9].

Fig. 11. TR-bridge test scheme. Fig. 10. DFT for integrity test of the TR-bridge.

for the cores connected to the AHB. Since the scan in and out cannot be performed simultaneously, twice scan-shifting time ). The is needed (noted in (4), (5), and (6) as the term values of the core wrapper registers whose length is greater than the bus width cannot be carried at once. Instead, a certain number of clocks are needed to transfer input and output is the time to apply a test wrapper values. where is the maximum patter for each AHB core with [10], is the number of 32-bit register set of scan-chain length, is the number of 32-bit the wrapper at the core PI side,

wire set of the wrapper at the core PO side, ned as

is de-

and each AHB core,

(5) is the total test-application time of [10] for is the number of test patterns, and

(6)

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Fig. 12. Timing diagram of scan test by the TR-bridge.

where is the total test-application time of [10] for each APB core. Additionally, seven more clocks are needed for test control and test bus-direction turnaround. The total test-application time for each AHB core with technique [3] can be summarized as shown in (5). The APB is used to interface low-speed peripheral devices, and according to [9], APB peripherals use two system clocks for each write or read transfer. Accordingly, the total testapplication time for each APB peripheral with technique [3] can be estimated as shown in (6), which is about two times longer than for the AHB core. 2) Test-Application Time for the Proposed Technique: The time required to apply a scan test vector and capture its response for an AHB core using the proposed technique is calculated by term (7). Due to the simultaneous scan shifting, the , and seven clocks are reduced to ve by is reduced to eliminating two bus-direction turnaround cycles. By bypassing the AHB-to-APB bridge in scan-test mode as in [13], the same test-application time can be achieved for both AHB and APB peripherals. Therefore, the total test-application time for both AHB and APB cores can be estimated as shown in (8). For this estimation, precise test-control sequences in the TR-bridge are not included. However, it is simply observed that the test-application time for each AHB core can be reduced by half, and the time for each APB core can be reduced to almost one quarter of the original amount required. (7) is the time to apply a test pattern for each AHB where core using the proposed technique (8)

is the total test-application time of the proposed where technique for both AHB and APB cores. H. Generality The proposed method can be adoptable to general SoCs of which the internal architectures are constructed satisfying the following congurations. 1) There is an on/off-chip bus bridge including both the slave component for the off-chip bus interface and the master component for the on-chip bus interface. This bridge serves as the TIC and test-stimulus-input interface between a SoC and an ATE. 2) There are separate write and read on-chip buses to provide on-chip test-stimulus-input and response-output paths, respectively. 3) There is an EBI component to provide the test-responseoutput interface to an ATE. The above architecture can be commonly found in various SoCs. For example, the separated write and read data buses are generally used for on-chip bus architecture to improve systemchip performance, and the EBI is frequently used to access the tightly coupled off-chip memory. Due to the general usage of the architecture, we do believe that our technique can be adoptable to different kinds of SoCs. IV. DESIGN EXPERIMENTS The AMBA-based SoC shown in Fig. 13 is adopted to evaluate the area overhead and test-application time for each embedded core [21]. Excluding the PLL, with full-scan scheme, 32 scan chains are inserted into each of the embedded cores to maximally utilize the scan in and out paths to an ATE in the AMBAbased SoC. For the functional test, the test data for design verication were used. For the structural test, the test patterns are

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Fig. 13. Example of AMBA-based system for experiments.

TABLE III CHARACTERISTICS OF CUT

generated through a commercial automatic-test-pattern-generator tool. The RTL codes are synthesized with 0.25- m-technology library. Among the main logics added in designing our TR AHB-PCI bridge, only a multiplexer between the PCI Write FIFO and AHB-master blocks of the TR-bridge lies on both normal and test paths. Thus, only negligible amount of delay overhead is introduced, and the correct operation of the SoC with AHB 200-MHz and PCI 66-MHz buses has been veried. The characteristics of each CUT [21] and the associated test information are described in Table III. Columns three and four present the area as the number of equivalent two-input NAND gates for each core. Columns ve, six, and seven show the number of PIs, POs, and D ip-ops, respectively. The maximum scan-chain length, number of test vectors, and fault coverage are given in columns eight, nine, and ten, respectively. In Table IV, the area overhead of the proposed HTIC is compared to that of the TIC [9], where the reduction ratio is formulated as

TABLE IV COMPARISON OF AREA OVERHEAD

Overhead of the Other Technique Overhead of Proposed Overhead of the Other Technique (9)

Although the savings in area is about 2% at the SoC level, the HTIC reduces the area by 76.23% as compared to the TIC [9]. This is accomplished by sharing the bridge functions as the test-control functions. Table V compares the functional test times for the key transactions shown in the rst column of this table. When functional verication patterns are applied, it is observed that an average of 35.72% of the test cycles are reduced in comparison with the TIC-based techniques [10], [13]. Structural-scan-testing times are compared in Table VI. As shown in the last column of the table, the scan test-application times for the AHB and APB cores are considerably reduced than the ones in [10] by an average of 43.27% and 69.37%,

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TABLE V COMPARISON OF FUNCTIONAL TEST TIME

REFERENCES
[1] Y. Zorian, E. J. Marinissen, and S. Dey, Testing embedded-core based system chips, in Proc. IEEE Int. Test Conf., Oct. 1998, pp. 130143. [2] J. F. Li, H. J. Huang, J. B. Chen, C. P. Su, C. W. Wu, C. Cheng, S. I. Chen, C. Y. Hwang, and H. P. Lin, A hierarchical test methodology for systems on chip, IEEE Micro, vol. 22, no. 5, pp. 6981, Sep./Oct. 2002. [3] E. Larsson and H. Fujiwara, System-on-chip test scheduling with recongurable core wrappers, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 3, pp. 305309, Mar. 2006. [4] D. Xiang, K. Li, H. Fujiwara, K. Thulasiraman, and J. Sun, Constraining transition propagation for low-power scan testing using a twostage scan architecture, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 5, pp. 450454, May 2007. [5] S. Hwang and J. A. Abraham, Test data compression and test time reduction using an embedded microprocessor, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 5, pp. 853862, Oct. 2003. [6] C. Su, R. F. Huang, and C. W. Wu, A processor-based built-in selfrepair design for embedded memories, in Proc. IEEE Asia Test Symp., Nov. 2003, pp. 366371. [7] I. Cota, L. Carro, M. Renovell, M. Lubaszewski, F. Azais, and Y. Bertrand, Reuse of existing resources for analog BIST of a switch capacitor lter, in Proc. Des., Autom. Test Eur. Conf., Mar. 2000, pp. 226230. [8] A. M. Amory, M. Lubaszewski, F. G. Moraes, and E. I. Moren, Test time reduction reusing multiple processors in a network-on-chip based architecture, in Proc. Des., Autom. Test Eur. Conf., Mar. 2005, pp. 6263. [9] AMBA Specication (Rev. 2.0), ARM, 1999. [10] C. Feige, J. T. Pierick, C. Wouters, R. Tangelder, and H. G. Kerkhoff, Integration of the scan-test method into an architecture specic coretest approach, J. Electron. Test., vol. 14, no. 1/2, pp. 125131, Feb. 1999. [11] C. Lin and H. Liang, Bus-oriented DFT design for embedded cores, in Proc. IEEE Asia-Pacic Conf., Dec. 2004, pp. 561563. [12] AHB Example AMBA System Technical Reference Manual, ARM, 1999 [Online]. Available: http://www.arm.com, ARM DDI 0170A [13] J. Song, P. Min, H. Yi, and S. Park, Design of test access mechanism for AMBA based system-on-a-chip, in Proc. IEEE VLSI Test Symp., May 2007, pp. 375380. [14] PCI Local Bus Specication, PCI Special Interest Group, 1998, rev. 2.2. [15] Z. Wang, Y. Ye, J. Wang, and M. Yu, Designing AHB/PCI bridge, in Proc. IEEE Int. Conf. ASIC, Oct. 2001, pp. 578580. [16] AMBA-AHB PCI Bridge IP Core Introductory Document PLDA Ltd [Online]. Available: http://www.plda.com/download/press_release/launch_ahb_pci_jan_2002.doc [17] AHB-PCI Bridge IP Core Introductory Document HiTech Global [Online]. Available: http://www.hitechglobal.com/ipcores/ahbpci.htm [18] ARM PrimeCell External Bus Interface (PL220), ARM, 2002 [Online]. Available: http://www.arm.com, ARM DDI 0249B [19] Excalibur Devices Hardware Reference Manual, ALTERA, 2002 [Online]. Available: www.altera.com, ver. 3.1 [20] AT91 ARM Thumb Microcontrollers, Atmel, 2002 [Online]. Available: http://www.atmel.com, AT91R40807 [21] J. Gaisler and E. Catovic, Gaisler Research IP Cores Manual. Colorado Springs, CO: Gaisler Res., 2005 [Online]. Available: http://www. gaisler.com/cms/, ver. 1.0.1 [22] IEEE Standard Testability Method for Embedded Core-Based Integrated Circuits, IEEE Std. 1500-2005, 2005, IEEE Computer Society, Test Technology Technical Council.

TABLE VI COMPARISON OF STRUCTURAL TEST TIME

respectively, and globally by 50.26%. Reference [13] and our TR-bridge, which provide concurrent scan shifting, result in similar application times, thus the results for [13] are not explicitly shown in this table. In the sequel, it is believed that the proposed technique will contribute in reducing the test-application time with minimal area overhead by providing concurrent scan in/out and bypass operation on the AHB-to-APB bridge during the structural test as well as fast functional test. V. CONCLUSION This paper proposes a design technique for an on/off-chip bus bridge to provide a more efcient TAM. Functional on-chip buses are fully exploited, and only simple logic is added to the on/off-chip bus bridge to utilize its functionality as a TIC. By discarding the bus-direction turnaround time and utilizing the EBI as the dedicated test-response-output channel, both functional and structural test times are signicantly reduced. Extensive case study has been performed for the AHB-PCI bridge. This technique can be generally applied to other types of on/offchip bus bridges to reduce test costs with minimal area overhead.

Jaehoon Song (S05) received the B.S. and M.S. degrees in computer science and engineering from Hanyang University, Kyeonggi-do, Korea, in 2000 and 2002, respectively, where he is currently working toward the Ph.D. degree in computer science and engineering in the Department of Computer Science and Engineering. In 2003, he was with the System-on-a-Chip (SoC) Design Center, Seoul National University, Seoul, Korea, where he was on the Development Staff in charge of platform-based design. His main research interests include design-for-testability, signal integrity, and low-power design. Mr. Song is currently a member of the Institute of Electronics Engineers of Korea and the Korea Information Science Society. He was the recipient of the Best Paper Award from the Korea Test Association at the Korea Test Conference in 2007.

SONG et al.: EFFICIENT SOC TEST TECHNIQUE BY REUSING ON/OFF-CHIP BUS BRIDGE

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Hyunbean Yi (S05M08) received the B.S., M.S., and Ph.D. degrees in computer science and engineering from Hanyang University, Kyeonggi-do, Korea, in 2001, 2003, and 2007, respectively. From 2002 to 2007, he was an Associated Researcher with Korea Electronics Technology Institute, Seongnam, Korea, where he was involved in the designing of high-speed communication chipsets. He is currently a Postdoctorate Fellow with the Department of Electrical and Computer Engineering, University of Massachusetts at Amherst, Amherst. His research interests include high-speed communication-system design, system-on-chip and network-on-chip testing, and design-for-testability.

Juhee Han received the B.S. and M.S. degrees in computer science and engineering from Hanyang University, Kyeonggi-do, Korea, in 2005 and 2007, respectively. She is currently with SAMSUNG Electronics, Yongin-si, Korea, where she is a development staff in charge of design-for-testability. Her main research interests include VLSI testing, signal integrity, and low-power design. Ms. Han is a member of the Institute of Electronics Engineers of Korea.

Sungju Park (M92) received the B.S. degree in electronics from Hanyang University, Kyeonggi-do, Korea, in 1983 and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Massachusetts at Amherst, Amherst, in 1988 and 1992, respectively. From 1983 to 1986, he was with Gold Star Company, Korea. From 1992 to 1995, he was with IBM Microelectronics, Endicott, NY, where he was a development staff in charge of boundary scan and LSSD scan design. Since then, he has been a Professor with the Department of Computer Science and Engineering, Hanyang University. His research interests are in the area of VLSI testing, including scan design, built-in self test, test pattern generation, fault simulation, and synthesis of test. Additional interests include graph theory and design verication. Prof. Park is a member of the Institute of Electronics Engineers of Korea, the Korea Information Science Society, and the Institute of Electronics and Information and Communication Engineers.