1-Bit Adder & 4-Bit Adder

Design a 1-bit adder using VHDL.

Design a 4-bit adder with 4x(1-bit adders) using VHDL.

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Simulation
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Hardware
On the FPGA itself.

Inputs:
A (1 bit) B (1 bit) Cin (1 bit)
Cout

Cin

Outputs
Sum = A xor B xor Cin Cout = AB + BC + AC
SUM

VHDL Code (1-Bit Adder)

entity <File Name> is Port ( <Define Inputs & Outputs>); end <File Name>; architecture <> of <Entity Name> is begin {Code implementation} end <>;

Notes
Libraries of the IEEE are analogous to the Libraries Import in JAVA. Entity: defines the Input (in) & Output (out) ports. Architecture: Comprises the Body of the code (Analogous to the Main Method in JAVA) STD_LOGIC means the value of this port will be 0 or 1 STD_LOGIC_VECTOR means the value of this port will be a Vector (array) of Zeros and Ones.

SUM <= A xor B xor C

<= : This sign says that the value of (A xor B xor C) is assigned to the SUM (similar to this arrow ) xor, and, or, not : Logical operators are written as words !!

Inputs A (4 bits) B (4 bits)

A3 B3 A2 B2 A1

Outputs Sum (4 bits) Cout (1 bit)

B1 A0 B0

Cout

1-Bit Adder
SUM 3

w3

1-Bit Adder
SUM 2

w2

1-Bit Adder
SUM 1

w1

1-Bit Adder

Cin= 0

SUM 0

Unit 4

Unit 3

Unit 2

Unit 1

Inputs A (4 bits) B (4 bits)

A3 B3 A2 B2 A1

Outputs Sum (4 bits) Cout (1 bit)

B1 A0 B0

Cout

1-Bit Adder

w3

1-Bit Adder

w2

1-Bit Adder

w1

1-Bit Adder

Cin= 0

SUM 3

SUM 2

SUM 1

SUM 0

Unit 4

Unit 3

Unit 2

Unit 1

< Index > : 3 2 1 0 A (4 bits) :0110 B (4 bits) :1011 --------------------------------Sum (4 bits) :1111 Cout (1 bit) :0010
A3 B3 A2 B2

A(3), A(2), A(1), A(0) B(3), B(2), B(1), B(0)

Sum(3), Sum(2), Sum(1), Sum(0)

Cout, w3, w2, w1

A1 B1 A0 B0

Cout

1-Bit Adder

w3

1-Bit Adder

w2

1-Bit Adder

w1

1-Bit Adder

Cin= 0

SUM 3

SUM 2

SUM 1

SUM 0

Unit 4

Unit 3

Unit 2

Unit 1

Entity Declaration
Input ports :

Specifying the circuits input & output ports.

A represents : A(0), A(1), A(2), A(3). B represents : B(0), B(1), B(2), B(3).

Output ports: SUM represents : SUM(0), SUM(1), SUM(2), SUM(3)

Cout entity adder4 is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); sum : out STD_LOGIC_VECTOR (3 downto 0); cout : out STD_LOGIC); end adder4;

Architecture

Component and Signal are placed above the Begin and End of the Architecture

Architecture

Component Object of the (1-bitadder) <Copy the bitadder entity inside the component> Analogous to the Constructor headings in Java, however its initializations (architecture) are in the bitadder file

Architecture
Signal w1, w2, w3 represents the Carry outs of the 1-Bit adder UNITs (1,2,3) Inside the (4 Bit Adder) w1, w2, w3 Temporary values

1.

In the Main Method / 4-Bit adder architecture

Student A = new Student (Name, ID); Student B = new Student (Name, ID);

2.

Calls the Constructor / Component

(VHDL) The Component represents the JAVA Constructor heading ONLY Public Student( N , ID )

1.

In the Main Method / 4-Bit adder architecture

Student A = new Student (Name, ID); Student B = new Student (Name, ID);

Label

2.

Calls the Constructor / Component

(VHDL) The Component represents the JAVA Constructor heading ONLY Public Student( N , ID )
JAVA : The Constructor has Inputs Only !!

Mapping with the Port

3.

The Constructor Body / 1-Bit adder file

The Sum and Cout values will be returned back to the units in the Main 4-Bit Adder Architecture.

* VHDL (Output/Returned values) are returned in the brackets.<PORT> * Java (Output/ Returned values) are stored to a NEW variable.

A3

B3

A2

B2

A1

B1

A0

B0

Cout

1-Bit Adder

w3

1-Bit Adder

w2

1-Bit Adder

w1

1-Bit Adder

Cin= 0

SUM 3

SUM 2

SUM 1

SUM 0

Unit 4

Unit 3

Unit 2

Unit 1

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