MDT2020(DF) Microcontroller Technical Specification

MDT2020(DF)
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology combines higher speed and smaller size with the low power and high noise immunity of CMOS. On chip memory system includes 2.0 K bytes of ROM, and 80 bytes of static RAM. u Addressing modes include direct, indirect and relative addressing modes u Power-on Reset u Power Edge-detector Reset u Sleep mode for power saving u 4 oscillator start-up time : 150 s, 20 ms, 40 ms, 80 ms u 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler u 4 types of oscillator can be selected by code options : RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator u On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely u 20 I/O pins with their own independent direction control
2. Features
The followings are some of the features on the hardware and software : u Fully CMOS static design u 8-bit data bus u On chip ROM size : 2 K words u Internal RAM size : 80 bytes (72 general purpose, 8 special registers) u 36 single word instructions u 14-bit instructions u 2-level stacks u Operating voltage : 2.3 V ~ 5.5 V u Operating frequency : 0 ~ 20 MHz u The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction.
3. Applications
The application areas of this MDT2020 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral etc.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 1
2005/6
VER 1.3
MDT2020(DF)
4. Pin Assignment DIP/ SOP/ SKINNY
RTCC Vdd N/C Vss N/C PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 /MCLR OSC1 OSC2 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 VSS RTCC VDD VDD PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PB4 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SSOP
28 27 26 25 24 23 22 21 20 19 18 17 16 15 /MCLR OSC1 OSC2 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5
5. Pin Function Description

Pin Name PA0~PA3 PB0~PB7 PC0~PC7 RTCC /MCLR OSC1 OSC2 Vdd Vss I/O I/O I/O I/O I I I O Function Description Port A, TTL input level Port B, TTL input level Port C, TTL input level Real Time Clock/Counter, Schmitt Trigger input levels Master Clear, Schmitt Trigger input levels Oscillator Input Oscillator Output Power supply Ground
P. 2
2005/6
VER 1.3
MDT2020(DF)
6. Memory Map
(A) Register Map Address 00 01 02 03 04 05 06 07 08~0F 10~1F 30~3F 50~5F 70~7F Description Indirect Addressing Register RTCC PC STATUS MSR Port A Port B Port C Internal RAM, General Purpose Register Internal Memory Select Register Internal Memory Select Register Internal Memory Select Register Internal Memory Select Register
(1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2
Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK
A10
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b6 b5 LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK
Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 2
2005/6
VER 1.3
MDT2020(DF)
(4) STATUS (Status register) : R3 Bit 0 1 2 3 4 6X5 Symbol C HC Z PF TF page Carry bit Half Carry bit Zero bit Power loss Flag bit Time overflow Flag bit Page select bit : 00 : 000H --- 1FFH 01 : 200H --- 3FFH 10 : 400H --- 5FFH 11 : 600H --- 7FFH 7 XX General purpose bit Function
(5) MSR (Memory Select Register) : R4
Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F
b7
b6
b5
b4
b3
b2
b1
b0
Read only 1 Indirect Addressing Mode (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register (8) PORT C : R7 PC7~PC0, I/O Register
P. 3
2005/6
VER 1.3
MDT2020(DF)
(9) TMR (Time Mode Register) Bit Symbol Prescaler Value Function RTCC rate WDT rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1 : 16 1:8 1 0 0 1 : 32 1 : 16 1 0 1 1 : 64 1 : 32 1 1 0 1 : 128 1 : 64 1 1 1 1 : 256 1 : 128 Prescaler assignment bit : 0 X RTCC 1 X Watchdog Timer RTCC signal Edge : 0 X Increment on low-to-high transition on RTCC pin 1 X Increment on high-to-low transition on RTCC pin RTCC signal set : 0 X Internal instruction cycle clock 1 X Transition on RTCC pin
2X0
PS2X0
PSC
TCE
TCS
(10) CPIO A, CPIO B, CPIO C (Control Port I/O Mode Register) The CPIO register is write-only 0, I/O pin in output mode; 1, I/O pin in input mode. (11) EPROM Option by Writer Programming: Oscillator Type RC Oscillator Oscillator Start-up Time 150 s,20ms,40ms,80ms 20 ms,40ms,80ms 20ms,40 ms,80ms 80 ms
HFXT Oscillator XTAL Oscillator LFXT Oscillator
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
P. 4
2005/6
VER 1.3
MDT2020(DF)
Power Edge Detect PED Disable Security bit Security weak Disable Security Disable Security Enable
PED Enable
7. Reset Condition for all Registers

Register CPIO A CPIO B CPIO C TMR IAR RTCC PC STATUS MSR PORT A PORT B PORT C Address 00h 01h 02h 03h 04h 05h 06h 07h Power-On Reset 1111 1111 1111 1111 1111 1111 --11 1111 xxxx xxxx 1111 1111 0001 1xxx 100x xxxx - - - - xxxx xxxx xxxx xxxx xxxx /MCLR or WDT Reset 1111 1111 1111 1111 1111 1111 --11 1111 uuuu uuuu 1111 1111 000# #uuu 100u uuuu - - - - uuuu uuuu uuuu uuuu uuuu
Note : u = unchanged, x = unknown, - = unimplemented, read as 0 # = value depends on the condition of the following table Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Status: bit 4 u 1 0 0 Status: bit 3 u 0 1 0
P. 5
2005/6
VER 1.3
MDT2020(DF)
8. Instruction Set
Instruction Code Mnemonic Operands Function No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return R R I Control I/O port register Store W to register Load register Load immediate to W Operating None 0WT 0WT,stop OSC WTMODE StackPC WCPIO WR Rt IW [R(0~3) R(4~7)]t R + 1t R + 1t W + Rt R Wt (R+/W+1t) R 1t R 1t R Wt I WW R Wt I WW R Wt /Rt R(n)R(n-1)A CR(7) R(0)C R(n)(n+1)A CR(0) R(7)C 0W 0R 0R(b) 1R(b) r TF, PF TF, PF None None None None Z None None Z None CA HCA Z CA HCA Z Z None Z Z Z Z Z Z Z C C Z Z None None Status
010000 00000000 NOP 010000 00000001 CLRWT 010000 00000010 SLEEP 010000 00000011 TMODE 010000 00000100 RET 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr CPIO STWR LDWI
LDR RA t
SWAPR RAt Swap halves register INCR R At Increment register
INCRSZ RA Increment registerAskip if zero ADDWR RA Add W and register t SUBWR RAt Subtract W from register DECR RAt DECRSZ RAt ANDWI I IORWI I XORWI I RRR RAt RLR CLRW CLRR BCR BSR R RA b R t A Decrement register
Decrement registerA skip if zero ANDWR RA AND W and register t AND W and immediate Inclu. OR W and immediate IORWR RAt Inclu. OR W and register XORWR RA Exclu. OR W and register t COMR RA t Complement register Rotate right register Rotate left register Clear working register Clear register Bit set RA b Bit clear
Exclu. OR W and immediate I WW
P. 6
2005/6
VER 1.3
MDT2020(DF)
Instruction Code Mnemonic Operands 0001bb brrrrrrr 0011bb brrrrrrr 100nnn nnnnnnnn 101nnn nnnnnnnn 110000 nnnnnnnn 110001 iiiiiiii 11001n nnnnnnnn Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive Exclusive Logic AND b t : : 0 1 R : C : HC : Z : / : x : i : n : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Dont care Immediate data ( 8 bits ) Immediate address BTSC BTSS LCALL LJUMP CALL RTWI i JUMP n Function Operating Skip if R(b)=0 Skip if R(b)=1 nPCA PC+1Stack nPC nPC, PC+1Stack Status None None None None None None None RA b Bit TestAskip if clear RA b Bit TestAskip if set n n n Long CALL subroutine Long JUMP to address Call subroutine
Return, place immediate to StackPC, W iW JUMP to address nPC
9. Electrical Characteristics
(A) Operating Voltage & Frequency Vdd R 2.3 V ~ 5.5 V FrequencyR Hz ~ 20 MHz 0 (B) Input Voltage @ V dd 5.0 V, Temperature25 J Port Vil Vih PA, PB, PC RTCC, /MCLR PA, PB, PC RTCC, /MCLR Min. Vss Vss 2.0 V 3.3 V Max. 1.0 V 1.0 V Vdd Vdd
P. 7
2005/6
VER 1.3
MDT2020(DF)
Threshold Voltage : Port A, Port B, Port C V th 1.5 V RTCC, /MCLR V il 1.3 V, V ih 3.0 V (Schmitt Trigger) (C) Output Voltage @ V dd 5.0 V, Temperature25 J, the typical value as followings : PA, PB, PC Port Ioh 20.0 mA Iol 20.0 mA Ioh 5.0 mA Iol 5.0 mA (D) Leakage Current @ V dd 5.0 V, Temperature25 J, the typical value as followings : Iil Iih (E) Sleep Current @WDTDisable, Temperature25 J, the typical value as followings : Vdd 2.3 V Vdd 3.0 V Vdd 4.0 V Vdd 5.0 V Vdd 5.5 V Idd 0.1 A Idd 0.1 A Idd 0.1 A Idd 0.1 A Idd=0.3 A 0.1A (Max.) 0.1 A (Max.) Voh 3.8 V Vol 0.5 V Voh 4.6 V Vol 0.13 V
@WDTEnable, Temperature25 J, the typical value as followings : Vdd 2.3 V Vdd 3.0 V Vdd 4.0 V Vdd 5.0 V Vdd 5.5 V Idd 1.0 A Idd 4.0 A Idd 10.0 A Idd 19.0 A Idd 35.0 A
P. 8
2005/6
VER 1.3
MDT2020(DF)
F) Operating Current Temperature25J, the typical value as followings :
(i) OSC TypeRC ; WDTEnable; @ V dd 5.0 V Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 3P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 20P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 100P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 300P 47.0 K 100.0 K 300.0 K 470.0 K Frequency (Hz) 11.8 M 5.9 M 1.3 M 685 K 225 K 140 K 6.1 M 3.1 M 760 K 355 K 120 K 75 K 1.9 M 1.0 k 220 K 100 K 35 K 22 K 950 K 520 K 95 K 45 K 15.0 K 9.6 K Current (A) 1.5 mA 835 A 280 A 190 A 140 A 132 A 865 A 513 A 195 A 155 A 125 A 120 A 355 A 225 A 130 A 116 A 110 A 108 A 210 A 155 A 115 A 106 A 102 A 100 A
P. 9
2005/6
VER 1.3
MDT2020(DF)
(ii) OSC TypeLF (C=20 p); WDTDisable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 5.5 V 32 K 2.8 A 5.0 A 11.0A 28.0 A 52.0 A 455 K X 36.0 A 63.0 A 100.0 A 130.0 A 1M
@2.6V 65
Sleep A 0.1 A 0.1 A 0.1 A 0.1 A 0.3 A
60.0 A 100.0 A 150.0 A 179.0 A
(iii) OSC TypeXT (C=20 p); WDTEnable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 5.5 V 1M 60.0 A 120.0 A 260.0 A 450.0 A 524.0 A 4M 150.0 A 280.0 A 500.0 A 740.0 A 890.0 A 10 M 350.0 A 590.0 A 950.0 A 1.50 mA 2.00 mA Sleep 1.0 A 4.0 A 10.0 A 19.0 A 35.0 A
(iv) OSC TypeHF (C=10 p); WDTEnable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 5.5 V 4M 150.0 A 330.0 A 575.0 A 900.0 A 1.00 mA 10 M 350.0 A 940.0 A 1.10 mA 1.60 mA 1.80 mA 20 M 630.0 A 1.10 mA 1.70 mA 2.60 mA 2.85 mA Sleep 1.0 A 4.0 A 10.0 A 19.0 A 35.0 A
P. 10
2005/6
VER 1.3
MDT2020(DF)
(G) Power Edge-detector Reset Voltage (Not in Sleep Mode), @ V dd 5.0 V Vpr 1.1~1.3 V Vpr
R
Vdd (Power Supply)
(H) The basic WDT time-out cycle time @Temperature25 J, the typical value as followings : Vdd =5.0 V, Temperature=25J,the typical value as followings:
Voltage (V) 2.3 3.0 4.0 5.0 5.5
Basic WDT time-out cycle time (ms) 28.0 25.0 21.5 19.5 18.5
P. 11
2005/6
VER 1.3
MDT2020(DF)
10. Port A ,Port B and Port C Equivalent Circuit
Working Register
D QB
Data I/P
I/O Control
CK
I/O Control Latch

Q
Port I/O Pin

D
Write
CK
Data O/P Latch

Q
Data Bus
QB D
Read
Data I/P Latch

CK
Input Resistor TTL Input Level
P. 12
2005/6
VER 1.3
MDT2020(DF)
11. MCLRB and RTCC Input Equivalent Circuit
R 1 K MCLRB
Schmitt Trigger
R 1 K RTCC
Schmitt Trigger
P. 13
2005/6
VER 1.3
MDT2020(DF)
12. Block Diagram
Stack Two Levels
EPROM 204814
RAM 72*8 Port A
Port PA0~PA3 4 bits
11 bits 11 bits 14 bits
Program Counters
Instruction Register
Special Register
OSC1 OSC2 MCLR D0~D7
Port B
Port PB0~PB7 8 bits
Oscillator Circuit
Instruction Decoder
Control Circuit
Data 8-bit
Power on Reset Power Down Reset Working Register ALU Status Register
Port PC0~PC7 8 bits
Port C
8-bit Timer/Counter
Prescale
WDT/OST Timer
RTCC
P. 14
2005/6
VER 1.3
MDT2020(DF)
13. External Capacitor Selection For Crystal Oscillator
@ V dd 3.0 V~ 5.0 V Osc. Type Resonator Freq. 20 MHz HF 10 MHz 4 MHz 10 MHz XT 4 MHz 1 MHz 1 MHz LF 455 K 32 K C1 5 pF ~10 pF 10 pF ~50 pF 10 pF ~50 pF 10 pF ~30 pF 10 pF ~50 pF 10 pF ~30 pF 3 pF ~5 pF 10 pF ~30 pF 10 pF ~20 pF C2 10 pF~30 pF 20 pF ~100 pF 20 pF ~100 pF 10 pF ~50 pF 20 pF ~100 pF 20 pF ~50 pF 3 pF ~5 pF 20 pF ~50 pF 15 pF ~30 pF
MDT2020 OSC1 OSC2
C1
C2
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range can be recommended for reference, but the higher capacitance also increases the start-up time.
P. 15
2005/6
VER 1.3

MDT2020(DF) Microcontroller Technical Specification

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MDT2020(DF)

5. Pin Function Description

(5) MSR (Memory Select Register) : R4

Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F

HFXT Oscillator XTAL Oscillator LFXT Oscillator

7. Reset Condition for all Registers

SWAPR RAt Swap halves register INCR R At Increment register

Exclu. OR W and immediate I WW

Return, place immediate to StackPC, W iW JUMP to address nPC

Sleep A 0.1 A 0.1 A 0.1 A 0.1 A 0.3 A

60.0 A 100.0 A 150.0 A 179.0 A

Vdd (Power Supply)

Voltage (V) 2.3 3.0 4.0 5.0 5.5

I/O Control Latch

Port I/O Pin

Data O/P Latch

Data I/P Latch

Input Resistor TTL Input Level

Stack Two Levels

RAM 72*8 Port A

Port PA0~PA3 4 bits

11 bits 11 bits 14 bits

OSC1 OSC2 MCLR D0~D7

Port PB0~PB7 8 bits

MDT2020 OSC1 OSC2

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