CMOS CURRENT-MODE ANALOG CIRCUIT BUILDING BLOCKS FOR RF DC-DC CONVERTER CONTROLLERS

J. Masciotti,1, L. Luu, D. Czarkowski

Department of Electrical and Computer Engineering Polytechnic University Brooklyn, NY 11201 USA

Department of Electrical Engineering Columbia University New York, NY 10027 USA

ABSTRACT
Conventional switch-mode dc-dc converters are operated at frequencies in the order of hundreds of kHz to single MHz. Switching frequencies in the order of tens of MHz would enable applications of RF converters in low power communications and computing integrated circuits with dynamic voltage scaling. Controllers for these converters would have to operate with a bandwidth in the GHz range. The maximum bandwidth for DSP controllers is around 100 MHz. It is expected that current-mode analog signal processing can achieve high enough bandwidths to control RF converters. Two fundamental building blocks for current mode analog integrated circuits are the current conveyor and the current comparator. This paper presents a high-speed current conveyor and current comparator that can be used to implement a feedback VLSI controller for RF dc-dc converters. Simulation results for both circuits show very high speed, low power consumption and small dc offset.

must be in the GHz range. Current mode analog integrated circuits, given an excellent treatment in [3], have very high bandwidth and consume little power. They have been shown to effectively provide feed-forward control for a 10MHz converter in [4]. The circuit in [4] uses second generation current conveyors and a current comparator as the two main building blocks. In order to obtain a fast enough controller, faster current conveyors and current comparators must be designed. The structure presented in [4] needs to be modified. Fig. 1 shows the modified feedforward controller for an RF buck converter. Some of the current conveyors are slightly modified negative and/or dual output conveyors, which are described in [3].

1. INTRODUCTION
RF dc-dc converters can be applied to reduce power consumption in mobile computing and communication devices. They can be used to perform dynamic voltage scaling in CMOS processors and to create a more efficient power amplifier for wireless communication transceivers such as WLAN cards. When these transceivers are transmitting data, most of the power is consumed by the output stage of the power amplifier. Typically these are class AB power amplifiers whose efficiency, , is given by:

V 0 , 4 VS

(1) Figure 1: Feedforward controller for an RF buck converter and current mode building blocks. The controller is composed of two pulsed integrator comparator systems that are switched at half of the intended frequency. Each pulsed integrator comparator systems output is sampled once per period in an alternating fashion via a multiplexer in order to maintain the original switching frequency. The duty ratio, D, for the buck converter is given by the equation (2), where Vref is the desired output voltage and VB is the battery or the supply voltage:
D= Vref VB .

where V0, is the amplitude or the output voltage and VS is the supply voltage. An RF dc-dc converter can be used to modulate the supply voltage to follow the envelope signal to be transmitted, which is the minimum allowable supply voltage, and thus maximize the efficiency. A 10 MHz boost converter was used to efficiently transmit a 1.22MHZ signal in [1]. In order to effectively transmit signals such as those associated with 802.11b WLANs which have data rates up to 11Mbs, a converter with a switching frequency close to 100 MHz is needed [2]. It is very difficult to control dc-dc converters at such frequencies because the controller bandwidth
1 Presently with the Department of Biomedical Engineering, Columbia University, New York, NY 10027, USA.

(2)

Fig. 2 shows a controller, which realizes both feed-forward and feedback, for the flyback converter. It uses 14 current conveyors to perform the analog signal processing required for PI feedback.

Figure 3: The High Speed Current Conveyor schematic and the values for each element.

2.2 Simulation Results

SPICE [7] simulations were performed for the designed current conveyor. Fig. 4 shows the simulation results.

Figure 2: Feedback-and-forth controller for flyback The remainder of this paper is organized as follows. In Section 2 we discuss the design of the high speed current conveyor. In Section 3 we discuss the design of the high speed current comparator. Finally, we summarize and comment on our results.

2. CURRENT CONVEYOR
2.1 Circuit Design
Fig. 1 shows the block diagram symbol for a second generation current conveyor. The conveyor is characterized by the fact that any voltage that appears at the Y terminal also appears at the X terminal and that any current that flows out of the X terminal also flows out of the Z terminal. Fig. 3 shows the transistor schematic for the high speed CMOS current conveyor that was designed in [5] using AMIs C5N process with parameters provided by [6]. Transistors M1 and M3 are designed with the same dimensions, the same dc bias current flowing through them, and the same dc drain source voltage (the same comment applies for M2 and M4, respectively). This means that any change in the voltage at Y will produce a change in current in M1 and thus the same change in current in M3, which in turn produces the same voltage at X that is at Y. Transistors M5 and M7 are designed so that the same current that flows in M5 and M3 and out of X terminal also flows in M7 and out Z terminal (again, what is true for M3, M5, M7 is also true for M4, M6, and M8, respectively). Resistors and bias voltages are designed to balance the operation of the circuit. As a rule, the conveyor was designed with a minimum gate area to reduce parasitic capacitance and maximize the bandwidth. It was, however, important to avoid small output resistances for transistors M7 through M10.

Figure 4: Simulated transfer functions of the designed current conveyor. (a) dc voltage. (b) dc current. (c) ac voltage, current, and total transfer functions Fig. 4(e) shows that when resistors are set for unity gain, the conveyor achieved a Y to Z bandwidth of 2.5 GHz. Table 1 summarizes the results shown in Fig 4. and compares them to those of previously designed circuits.

Table 1: Circuit Comparisons

The current comparator consists of a current amplifier (M1-M4 and Rp), a Class B output stage (M7-M8), and three CMOS inverters (M5-M6, M9-M12). The proposed design is a modified version of the simple current comparator [10], with an added current amplifier and an extra pair of inverters compared to the original design. The current amplifier enhances the degrading response of the current comparator for small input currents. It consists of two current mirrors. To minimize power consumption, the widths of M1-M4 were kept to a minimum while the lengths were adjusted to achieve a desired current gain. After matching the currents through M1 and M2, the currents through M3 and M4 were matched as well. An additional Rp was added to minimize the dc current offset. M1-M4 dimensions were chosen while taking into consideration the inverse relationship between the gain and the 3-dB frequency of the current amplifier. M5 and M6 are in the positive feedback loop and serve to invert the incoming signal. In order to reduce parasitic capacitances while allowing the inverter to draw more current for a faster charge, the lengths of M5 and M6 were minimized and the widths were adjusted. The dead-band region created by M7 and M8 is minimized by setting the lengths and widths of both transistors to a minimum. M9-M12 are a pair of CMOS inverters to output a rail-to-rail resulting signal with a negligible delay time. The component values are shown in Table 2. Table 2: Component values for the current comparator

The newly designed circuit exhibits a very high bandwidth of 2.5 GHz and small dc offsets. Its parasitic input resistance and output resistance were calculated in [5] to be 181K and 169K respectively. Fig. 5 shows its ability to follow a 100 MHz triangular wave, similar to the saw-tooth it must follow in the controller application. A corresponding current comparator is discussed in the next section.

Figure 5: Simulating a .1V 100 MHz triangular wave.

Transistor M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12

Type P N P N P N N P P N P N

W (um) 0.36 0.36 0.36 0.36 1.08 0.36 0.36 0.36 1.08 0.36 1.08 0.36

L (um) 0.48 2.04 0.24 0.6 0.24 0.24 0.24 0.24 0.24 0.24 0.24 0.24

Voltage V+ VResistor Rp

(V) 1.25 -1.25 Ohms 124.9

3. CURRENT COMPARATOR
3.1 Circuit Design
A current comparator is an analog current-mode signal processing circuit that takes a current (Iin) as an input and outputs a voltage signal (Vout). When Iin flows into the circuit, Vout is high. When Iin flows out of the circuit, Vout is low. The current comparator serves as one of the critical components of the converter controller, which converts the current values into width-modulated pulses fed to the converter. Various current comparators have been described [10-12]. The proposed new high-speed, low dc offset, and low power consumption CMOS current comparator is shown in Fig. 6.

3.2 Simulation Results

The new current comparator was simulated using TSMC 0.25um CMOS technology parameters [6] with 2.5 V power supply. Fig. 7 shows the input square-wave current change between 0.1 uA and -0.1 uA, as well as the transient waveform of the output voltage and the instantaneous power of the proposed comparator. Incidentally, the rise time and fall time delays are both 2.72ns. The average power consumption is 460uW. To our knowledge, the simulation results of the proposed current comparator are better than existing comparators to date. When the circuit in [10] was simulated using the parameters in [6], the delay was 12ns for a .1uA wave and 12ns for a 1uA wave. A major concern when simulating the current comparator is to observe its response to low inputs. A large delay for small signals can jeopardize the performance of the current

Figure 6: New CMOS Current Comparator.

comparator. A varying amplitude saw-toothed input current was simulated to verify if the comparator can output the corresponding duty ratios intended for pulse width modulation (PWM). The output graph in Fig. 8 demonstrates that the comparator can perform PWM.

offer faster responses than those reported previously reported in the literature. The values for the resistors shown in the architecture of the controller should be designed to compensate the parasitic resistances of the conveyors and although the parasitic resistances put a limit on the gain, the widths of M7 and M8 can be increased to compensate. Transistor matching was done according to level 7 SPICE parameters, so the designs are process dependent. Even though layout was not performed and the blocks were designed in different CMOS technologies, the authors are confident that the controller can be implemented on a single chip and effectively control an RF dc-dc converter.

5. ACKNOWLEDGEMENTS
Mr. Luus work was supported by the National Science Foundation Grant NSF REU EEC-9619749.

6. REFERENCES
[1] Hanington G. , Chen P.F., Asbeck P. M., Larson L. E., High-Efficiency Power Amplifier Using Dynamic Power Supply Voltage for CDMA Applications, IEEE Trans. on Microwave Theory and Techniques, August 1999. [2] Biernacki J., and Czarkowski D., Radio Frequency Dc-Dc Flyback Converter, proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS2000), Vol. 1, pp. 94-97. [3] Toumazou C., Lidgey J. and Haigh D., Editors, Analogue IC design: The current-mode approach IEE Circuits and Systems Series 2, Editorial P. Perengrinus. 1991. [4] E. Alarcn, G. Villar, E. Vidal, H. Martnez and A. Poveda, General-purpose one-cycle feedforward controller for switching power converters: A high-speed current-mode CMOS VLSI implementation proceedings of the 44th IEEE Midwest Symposium on Circuits and Systems (MWSCAS01), Dayton, Ohio, USA, August 2001, pp. 290293. [5] Masciotti, J., CMOS Current Conveyor for RF DC-DC Converter Controllers, Masters Thesis, Polytechnic Univ. Brooklyn, NY. 2002. [6] MOSIS, http://www.mosis.org [7] SPICE OPUS, http://www.fe.uni-lj.si/spice/welcome.html. [8] Popovi J., Pavasovi A., Vasiljevi D., Low-power High Bandwidth CMOS Current Conveyor, proceedings of the 21st Int. Conf. on Microelectronics (MIEL97), Vol. 2, Ni, Yugoslavia, pp. 693-696. [9] Cha H.W, Watanabe K., Wideband CMOS current conveyor, Electronics Letters, Vol. 32, No. 14, pp. 12451246, 1996. [10] H. Trff, Novel Approach to High Speed CMOS Current Comparators, Electron. Lett., vol. 28, no. 3, pp. 310-312, 1992. [11] Lin H., Huang J., Wong S., A Simple High-Speed Low Current Comparator, IEEE Intl. Symposium on Circuits and Systems ISCAS2000, Geneva, Vol. 2 pp. 713-716 [12] Chen L., Shi B., Lu C., A High Speed/Power Ratio Continuous-Time CMOS Current Comparator, proceedings of the 7th IEEE Intl. Conf. on Electronics, Circuits and Systems ICECS2000, pp. 883-886.

Figure 7: The waveforms of the input current (a), the output voltage (b), and the instantaneous power (c).

Figure 8: The waveforms of the varying amplitude sawtoothed input current (a) and the output voltage (b). Since the converter controller will multiplex two current comparators, the relevant regions for each comparator alternate every switching frequency. The remaining regions are irrelevant to the comparators performance, hence, the shaded regions in Fig. 8(b).

4. CONCLUSIONS
This paper developed a new structure for a feedback-and-forth RF dc-dc converter controller. The two circuit building blocks needed to implement the controller structure were designed. A new high speed CMOS Current Conveyor and a new high speed Current Comparator were designed and simulated. Both circuits