CN 303 MICROPROCESSOR AND MICROCONTROLLER

Lecture#9:Interrupts

Introduction
A computer must execute one of the collection of special routines whenever certain conditions exits within a program or the microcomputer system. For instance the microcomputer system should give response to devices such as a keyboard, mouse and other components when they request for a service.

Introduction
The most common method is polling, where the CPU tests each device in sequence and in effect ask each one if it needs communication with a PROCESSOR. But polling requires that large portion of the I/O program to continuous monitor the peripheral devices in a loop. Polling affects system throughput ,thus affecting number of tasks and cost effectives of a microcomputer system.

Introduction
A more desirable method is the one that allows the CPU to execute I/O programs and stop peripheral devices when its told by the peripheral devices. In effect this method provides external asynchronous input that inform the CPU to complete the current instruction and fetch a new routine that serves a requesting device. Once this routine completes the CPU resumes where it left off.

Introduction
This method that causes the CPU to finish the current instruction and fetch the new routine that serves the requesting device is called INTERRUPT METHOD. It is easy to see how throughput increases to enhance cost effectiveness of microcomputer systems through this method.

Introduction
Microcomputer systems allow execution of special routines called INTERRUPT SERVICE ROUTINES when they receives an interrupt. Remember an interrupt cause a processor to stop executing a normal program and call a special routine that services an interrupt.

Ways of interrupting a normal program

Normal program can be interrupted in three ways; By external signal By special instruction in the program By occurrence of some condition Interrupts caused by external signal are called HARDWARE INTERRUPTS. Those by special instruction or by condition occurrence are called SOFTWARE INTERRUPTS.

Hardware interrupts These are caused by external signals applied to the NonMaskable Interrupt (NMI) input pin or the interrupt(INTR) input pin.

Software interrupts
These are caused by a special instruction INT n(integer) or by a condition produced in the 8086 by execution of an instruction(Divide by zero etc).

Note that : An interrupt service

routine(ISR) is executed whenever a processor receives an interrupt but control is returned to the interrupted program when the ISR completes.

Interrupt cycle of 8086

At the end of each instruction cycle 8086 checks to see if there is any interrupt request , if so 8086 responds by doing the followings;
1. It decrements SP by 2 and pushes the flags on the stack 2. It disables the INTR interrupt pin by clearing the IF flag 3. It resets the trap flag(TF)

Interrupt cycle of 8086

4. It decrements SP by 2 again and pushes CS on the stack 5. It decrements SP by 2 again and pushes IP on the stack 6. It executes an indirect far jump to transfer control to the ISR by loading the CS and IP values as start a address of the ISR 7. Now the ISR is running 8. Finally an IRET instruction returns control to the main program

ISR starting address

Question
How does a processor get the starting address of the ISR?

Answer
From the INTERRUPT VECTOR TABLE

In an 8086 system the 1st 1Kbyte of memory from 00000H to 003FFH is reserved for storing the starting addresses of ISRs.

ISR starting address

This memory block is called the INTERRUPT VECTOR (POINTER) TABLE. Since 4 bytes are required to store CS and IP values for each ISR,the table can hold the starting addresses for 256 ISRs. The starting address for each ISR is extracted from the IVT using an integer number a part of the INTR n instruction.

ISR starting address

Note that : An integer is an index to the IVT and points to the 1st byte of the starting address. Figure 11.1 shows typical usage of interrupts in a typical system. Figure 11.2 (a)shows how the 256 interrupt pointers or vectors are arranged in the memory to create the IVT. Figure 11.2(b) gives the contents of an interrupt vector.

Figure 11.1 Interrupt usage in a typical system

Figure 11.2(a) and (b)

Index 32-255 5-31 4 3 2 1 0 ADDRESS 080H-3FFH 014H-07FH 010H-013H 00CH-00FH 008H-00BH 004H-007H 000H-003H IVT Type 32-255 User interrupt vectors Type 5-31 Reserved Type 4 overflow Type 3 1-Byte breakpoint Type 2 Non-maskable Type 1 Single step Type 0 Divide error

8086 IVT
Only five have explicit definitions such as divide by zero and non-maskable interrupt. The next 5-31 are reserved by Intel for use in future microprocessors. The upper 32-255 are available for hardware and software interrupts.

Interrupt vector and IVT

When an 8086 responds to an interrupt, it automatically goes to the specified location in the IVT using the supplied interrupt vector from software or hardware as an index to the IVT to retrieve the starting address of the ISR. So the user has to load these starting addresses for different ISRs at the start of the program.

8086 Interrupt Types

Divide by zero(Type 0)
When a quotient from either a DIV and IDIV instruction is too large to fit in the result register or zero;8086 automatically execute type 0 interrupt.

Single Step Interrupt(Type 1)

When a processor receives this interrupt it executes next instruction and wait for further instruction from a user

8086 Interrupt Types

Then user can examine contents of memory locations and registers, if they are correct user can tell the processor to execute the next instruction. This feature is useful for debugging programs.

An 8086 is used in this mode by setting the Trap flag, once the TF is set an 8086 automatically execute Type 1 interrupt after executing each instruction. But TF can be set or clear by manipulating the flag register contents in memory using PUSHF instruction.

8086 Interrupt Types

Non Maskable Interrupt(Type 2)
Its activated by low to high transition on 8086 NMI input pin. Can not be disabled by any instruction

Breakpoint Interrupt(Type 3)
Is produced by execution of INT 3 instruction, inserting a breakpoint causes a system to execute instructions up to breakpoint, and then goes to the breakpoint procedure.

8086 Interrupt Types

In the breakpoint procedure you can write a program to display register contents, memory contents and other information that is required to debug your program. Can insert as many breakpoints as you can

Overflow Interrupt(Type 4)
Checks overflow condition after any signed arithmetic operation in the system and then executes the INTO or INT 4 instruction.

8086 Interrupt Types

To detect overflow in your programs put an INTO instruction after the arithmetic instruction in the program, if OF is set indicating an overflow error, the 8086 will execute a type 4 interrupt after executing the INTO instruction otherwise INTO will simply function as NOP if OF is not set.

8086 Interrupt Types

Software Interrupts Type 0-255
The INT n instruction can be used to cause the 8086 to execute one of the 256 possible interrupt types. For instance INT 2 executes an NMI interrupt service routine, allowing to test the NMI routine without the need to apply an external signal to the NMI input pin. From these interrupts desired routines from different programs in a system e.g. BIOS in IBM PC can be called.

8086 Interrupt Types

Software Interrupts Type 0-255
IBM PCs ROM has a collection of routines, each performing some specific function such as reading a character from the keyboard, writing character to CRT. This routines a referred to as Basic Input Output System or BIOS. An 8086 interrupt cycle is similar for all interrupts.

8086 Interrupt Types

Maskable Interrupt(INTR)
Is level-sensitive interrupt activated by applying logic 1 at the INTR input pin. Its set by an external event and cleared inside the interrupt service procedure. Once accepted by the 8086 the INTR input is automatically disabled and re-enabled by the IRET instruction at the end of the interrupt service procedure.

8086 Interrupt Types

The microprocessor responds to the INTR input by pulsing the INTA output in anticipation of receiving an interrupt vector type number on data bus connection D7-D0. Figure 11-8 shows the timing diagram for the INTR and INTA pins of the microprocessor.

Figure 11-8 shows the timing diagram for the INTR and INTA pins of the microprocessor.

8086 Interrupt Types

There are two INTA pulses generated by the system that are used to insert the vector type number on the data bus.

Interrupt Priorities
Priority 1 Interrupt Divide error and all software interrupts ( Int n) except those listed bellow Priority Level HIGHEST

2 3 4

NMI INTR Single step

LOWEST

Interrupt Priorities
To enforce priorities;
An 8086 clears the interrupt flag automatically as part of responding to an interrupt. This prevents a signal on INTR input from interrupting a higher priority ISR. But an 8086 allows a signal on NMI input to interrupt higher priority interrupt.

Note that : An 8086 checks internal interrupts before it checks external interrupts.(Divide error and NMI example)

Expanding Interrupt Structure

Interrupts are needed for variety of applications. Each application requires a separate interrupt input pin. But an 8086 gives only two interrupt input pins : NMI and INTR. For applications with multiple sources of interrupts an external device called a priority interrupt controller(PIC) is used.

Connection between 8086 and 8259

Features of 8259
1. It can manage 8 priority interrupts, equivalent to providing 8 interrupt pins on the processor INTR input pin. 2. It is possible to locate vector table for these additional interrupts anywhere in the memory map . However, all 8 interrupts must be spaced at the interval of 4 or 8 locations. 3. By cascading 8259s it is possible to get 64 priority interrupts.

Features of 8259
4. An interrupt mask register makes it possible to mask individual interrupt request. 5. Can be programmed to accept either the level triggered or the edge triggered interrupt request. 6. User can get the information of pending interrupts, in-service interrupts and masked interrupts from 8259A. 7. The 8259A is designed to minimize software and real time overhead in handling multi-level priority interrupts.

Pin out of the 8259A PIC

8259A Pin out and functions

WR
The write input connects to either the lower or upper write strobe signal in a 16-bit system or any other bus write strobe in any size system.

RD
The read input connects to the read strobe signal.

INT
The interrupt output connects to the INTR pin on the microprocessor from the master, and is connected to a master IR pin on a slave.

8259A Pin out and functions

INTA
Interrupt acknowledge is an input that connects to the INTA signal on the system. In a system with a master and slaves, only the master INTA signal is connected.

A0
The A0 address input selects different command words within the 8259A.

8259A Pin out and functions

CS
Chip select enables the 8259A for programming and control.

CAS0-CAS2
The cascade lines are used as outputs from the master to the slaves for cascading multiple 8259As in a system.

8259A Pin out and functions

SP/EN
Slave program/enable buffer is a dual-function pin. When the 8259A is in buffered mode, this pin is an output that controls the data bus transceivers in a large microprocessor-based system. When the 8259A is not in buffered mode, this pin programs the device as a master (1) or a slave (0).

Block diagram of 8259A

Block diagram of 8259A

It includes eight blocks;
1. 2. 3. 4. 5. 6. 7. 8. Data bus buffer Read/write logic Control logic Interrupt request register(IIR) Interrupt service register(ISR) Interrupt mask register(IMR) Priority resolver and Cascade buffer

Block diagram of 8259A

Data buffer
Allows the 8086 to send control words to the 8259A and read a status word from the 8259A. The 8 data bus also allows the 8259A to send interrupt types to the 8086.

Read/Write logic
The RD and WR control the data flow on the bus when the device is selected by asserting its chip select(CS) input low.

Block diagram of 8259A

Control logic
This block as an input and output line. If the 8259A is properly enabled the interrupt request will cause it to assert its INT output pin high, if this pin is connected to the INTR pin of the 8086 and if the IF flag is set then this high signal causes the 8086 to respond to the interrupt request.

Block diagram of 8259A

Interrupt Request Register
Store 8 bits to indicate interrupt inputs(IR0IR7) requesting a service. If respective bit is 1-requesting service otherwise if respective bit is 0-not requesting any service.

Interrupt Service register

Stores input lines(as bits) that are currently being serviced.

Block diagram of 8259A

Interrupt Mask Register
Stores interrupt lines(as bits) that are currently masked. This register can be programmed by an OCW(details later). An interrupt that is masked by software will not be recognized and serviced even if it set in the IRR.

Block diagram of 8259A

Priority resolver
Determines the priority of bits set in the IRR. The bit with the highest priority is set in the ISR during the INTA input.

Block diagram of 8259A

Cascade buffer comparator
Generates control signals necessary for cascade operations and Buffer-Enable signals. Allows cascading of the 8259 with other 8259s to expand interrupt handling capacity to 64 levels. If 8259s are cascaded first is a master and others are slaves. The 8259 can be set as a master or slave by the SP/EN pin.

Block diagram of 8259A

CAS0-CAS1
Selects 1 out of 8 possible slaves. For master these pins act as outputs and as inputs for slaves. When a master receives interrupt request from other slaves(8259s) in response to the first INTA it generates three bits on the CAS0CAS2 lines to select 1 out of 8 possible slaves.

Block diagram of 8259A

The slaves(8259s) accept these signals and compare them with the code assigned to them during initialisation. The slave selected(which had originally placed an interrupt request to the master) then puts out the address of the interrupt service routine during the second and third INTA pulses from the CPU.

Block diagram of 8259A

SP/EN(Slave Program/Enable Buffer)
This signal specifies if the 8259 acts as a master when it is HIGH otherwise its grounded if it acts as the slave in non-buffered mode. In buffered mode when the 8259 is sending the data in response to INTA data can not be accessed by the CPU(bse data bus buffer are disabled during interrupt processing in large systems using buffers to drive the data bus) Therefore this signal is used as an output to enable data bus buffers of the system.

Interrupt Sequence
The events occurs as follows;
1. One or more INTERRUT REQUEST lines(IR0-IR7) are raised high, setting the corresponding IRR bit(s). 2. The priority resolver checks the three registers : IRR for interrupt request,IMR for masking bits and ISR for interrupt request being served. It resolves the priority and sets the INT high when appropriate. 3. The CPU acknowledges the INT and responds with an INTA pulse.

Interrupt Sequence
4. Upon receiving an INTA from the CPU,the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259 does not drive data bus during this cycle. 5. The 8086 initiates a second INTA pulse, during this pulse the 8259 releases a 8-bit pointer(interrupt type) onto the data bus where it is read by the CPU.

Interrupt Sequence
4. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of the second INTA pulse.Otherwise,the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine. 5. Note that : The priority modes can configured by the programmer dynamically at any time during the main program to define the complete interrupt service structure based on system requirements.

Priority Modes and Other Features

The various modes of operation of the 8259 are;
a) b) c) d) Fully nested mode Rotating priority mode Special masked mode and Polled mode

Fully nested mode

After initialisation the 8259 operates in fully nested mode so it is called a default mode. It continues to operate in fully nested mode until the mode is changed through Operation Command words. In this mode IR0 has a highest priority and IR7 has lowest priority.

Fully nested mode

On the acknowledgement of an interrupt the 8259 in this mode it will set the corresponding bit in ISR to prevent all interrupts of the same or low level and it will accept higher priority interrupt requests , then the vector address corresponding to this interrupt is sent.

Fully nested mode

The bit in ISR will remain set until EOI is issued by the microprocessor at the of the interrupt service routines. But if AEOI(Automatic End of Interrupt) bit is set , the bit in the ISR resets at the trailing edge of the last INTA.

Special Fully Nested Mode(SFNM)

In FNM,on the acknowledgement of an interrupt, further interrupts from the same level are disabled. But in large systems with cascaded 8259s and where interrupt levels within each slave have to be considered. FNM disables further interrupts on the same input level in the master.

Special Fully Nested Mode(SFNM)

Such that if the slave places an interrupt input to the master further interrupts to the slave will cause the slave to place interrupts to the master on the same input and these will be neglected if the master is operating in FNM. SFNM avoids this problem, and its set using ICW4.

Special Fully Nested Mode(SFNM)

It is similar to FNM except for the following differences;
1. The slave is allowed to place further requests even if the interrupt request is being serviced.(further requests are of higher priority than request currently being serviced and are recognized by the master which initiates interrupt requests to the CPU)

Special Fully Nested Mode(SFNM)

2. Before the master serves another ISR a non-specific EOI must be sent to the slave to determine if it was the only interrupt to the slave.
If it is not the same interrupt request level input to the master must be serviced again because the slave as presented more than one interrupt requests and an EOI must not be sent to the master.

Special Fully Nested Mode(SFNM)

Otherwise if no more interrupt requests from the slave an EOI interrupt is sent to the master which now it is free to serve the next slave.

Rotating Priority Mode

Two types; 1. Automatic rotation In this mode a device after being serviced , receives a lowest priority. Assuming IR3 has just been serviced , it will receive the seventh priority.

Rotating Priority Mode

2. Specific rotation In this mode a device after being serviced, the lowest priority can be assigned to any device.

Special Mask Mode

In this mode , if any interrupt is in service then the corresponding bit remains set in ISR and lower priority interrupts are inhibited But the interrupt service routines;
Can dynamically alter the priority structure Only by inhibiting further interrupts in the same level and allowing interrupts form all other levels(lower and higher) during its execution under software control that are not

Special Mask Mode

That is any interrupt can be selectively enabled by loading the mask register For example a routine may inhibit lower priority requests for a portion of its execution but enables some of them for another portion.

Poll Mode
In this mode the INT output is not used. Instead the microprocessor checks the status of interrupt requests by issuing a poll command. After issuing a poll command the microprocessor reads contents of 8259A and the 8259A provides polled word and sets ISR bit of highest priority active interrupt request.

Polled word
I X X X X W2 W1 W0

I=1One or more interrupt request activated I=0No interrupt request activated W2 W1 W0Binary code of highest priority active interrupt request

Programming the 8259A

The 8259A requires two types of command words;
1. Initialization Command Words(ICWs) and 2. Operational Command Words(OCWs)

Programming the 8259A

The 8259A can be initialized with 4 ICWs,the first two are compulsory and the other two are optional based on modes being used. The ICWs must be issued in a given sequence. After iniatilization,the 8259A can be set up to operate in various modes by using three different OCWs.

Programming the 8259A

However OCWs need no specific issuing sequence.

Flow Chart for 8259 Initialization

Initialized Command Word 1 (ICW1)

Initialized Command Word 1 (ICW1)

A write command issued to the 8259 with A0=0 and D4=1 is interpreted as ICW1, which starts the initialization sequence. It specifies;
1. Single or multiple 8259A in the system 2. 4 or 8 bit interval between the interrupt vector locations 3. Edge triggered or level triggered interrupts 4. ICW4 is needed or not

Initialized Command Word 2 (ICW2)

Initialized Command Word 2 (ICW2)

A write command following ICW1,with A0=1 is interpreted as ICW2. It is used to load the high order byte of the interrupt vector address of all the interrupts.

Initialized Command Word 3 (ICW3)

Initialized Command Word 3 (ICW3)

ICW3 is required only if there is more than one 8259 in the system, and if they are cascaded ICW3 is used to load a byte to the 8259 master or slave. The byte to be loaded as an ICW3 for 8259 master or a slave is as shown in the previous slide.

Initialized Command Word 3 (ICW3)

When loaded to the8259 master each bit in ICW3 indicates whether the respective IR input of the master as a slave attached to it. When loaded to the 8259 slave, bits D0-D2 of ICW3 are used to assign a slave identification code(slave ID) to the 8259.

Initialized Command Word 4 (ICW4)

Initialized Command Word 4 (ICW4)

It is loaded if the D0 bit (IC 4) is set. It specifies;
1. Whether to use fully nested mode or non-fully nested mode 2. Whether to use buffered mode or non-buffered mode 3. Whether to use Automatic EOI or Normal EOI 4. CPU used,8086/8088 or 80810

From ICWs to OCWs

After initialization the 8259 is ready to process interrupt requests. However during operation , it might be necessary to change the mode of processing the interrupts. Operation Command Words(OCWs) are used for this purpose. OCWs may be loaded anytime after the 8259s initialization to alter the priority modes.

Operation Command Word 1 (OCW1)

Operation Command Word 1 (OCW1)

A write command to 8259 with A0=1(after ICW2) is interpreted as OCW1. OCW1 is used for enabling or disabling the recognition of specific interrupt requests by programming the IMR. M=1 indicates that the interrupt is to be masked and M=0 indicates that it is to be unmasked as shown in the previous slide.

Operation Command Word 2 (OCW2)

Operation Command Word 2 (OCW2)

A write command with A0=1 and D4,D3=00 is interpreted as OCW2. R(Rotate),SL(Select-Level),EOI bits control the Rotate and End of Interrupt Modes and combinations of the two. L2-L0 are used to specify the interrupt level to be acted upon when the SL bit is active.

Operation Command Word 3 (OCW3)

Operation Command Word 3 (OCW3)

OCW3 is used to read the status of the registers, and to set or reset the Special Mask and Polled Modes. The status of the Interrupt Request Register ; In-Service Register and Interrupt Mask Register of the 8259 may be read by issuing appropriate Read Commands as described bellow.

IRR status Read

An OCW3 with RR(Read Register)=1 and RIS(Read ISR)=0 set up the 8259 for a status read of the interrupt request register(IIR). The next Read commands(all) with A0=1 cause the 8259 to send IRR status word when the 8259 is not in the Polled Mode after its set for IRR status read operation.

ISR status Read

An OCW3 with RR(Read Register)=1 and RIS(Read ISR)=1 set up the 8259 for a status read of the In-Service Register(ISR). A subsequent Read command issued to the 8259 will cause the 8259 to send ISR status word onto the data bus.

IMR status Read

A Read command issued to the 8259 with A0=1(with RD,CS=0) causes the 8259 to put out the contents of the Interrupt Mask Register(IMR). OCW3 is not required for a status read of the IMR.

IMPORTANT NOTE
The sequence shown on the flow chart must be followed to initialize 8259A. According to the flow chart an ICW1 and an ICW2 must be sent to any 8259A in the system. If a system has any slave 8259s(cascade mode) then an ICW3 must be sent to the master, and difference ICW3 must be sent to the slave.

IMPORTANT NOTE
If the system is an 8086,or if you want to specify certain special conditions , then send ICW4 to the master and to each slave.

8259A Interfacing
Fig 11.4 shows how an 8259A can be interfaced with the 8086 microprocessor system in minimum mode. The 74LS138 address decoder will assert the CS input to the 8259A when an I/O base address is FFF0H or FFF2H on the address bus. The A0 input of the 8259A is used to select one of the two internal addresses in the device.

8259A Interfacing(Fig 11.6)

8259A Interfacing
Since A0 is connected to system line A1,so the system internal addresses are FFF0H and FFF2H. Data lines of an 8259A are connected to the lower half of the system data bus, because the 8086 expects to receive interrupt types on these lower eight data lines. RD and WR signals are connected to the system RD and WR lines.

8259A Interfacing
The interrupt request signal INT from the 8259A is connected to the INTR input of the 8086 and INTA from 8086 is connected to INTA on the 8259A. Since we are using a single 8259A in the system SP/EN pin is tied high and CAS0CAS2 lines are left open. The 8 IR inputs are available for interrupt signals.

8259A Interfacing
Note that; 1. Unused IR inputs should be tied to ground so that a noise pulse cannot accidentally cause an interrupt. 2. In maximum mode RD and INTA signals of 8259A are connected to the IORC,IOWC and INTA lines of 8288 bus controller.

Cascading the 8259s

8259As can easily be interconnected to get multiple interrupts. Fig 11.7 shows how 8259A can be connected in the cascade mode. In cascade mode one 8259A is configured as Master and other 8259As as Slaves. In this figure 8259A-1 is the Master and others are slaves.

Cascading the 8259s(Fig 11.7)

Cascading the 8259s

Each slave is identified by the number which is assigned as part of its initialization. Since the 8086 as an INTR input, only one of the 8259A INT pins is connected to the 8086 INTR pin. The 8259A connected directly in to the 8086 INTR pin is referred as the master. The INT pins from other 8259A(Slaves) are connected to the IR inputs of the 8259A master.

Cascading the 8259s

The INTA signal is connected to both master and slave 8259A. Cascade pins CAS1-CAS2 are connected from the master to the corresponding pins of the slave. For master these pins function as outputs and as inputs for slaves. The signal is tied high for the master and it is grounded for slaves.

Cascading the 8259s

Note that;
Each 8259A has its own addresses so that command words can be written to it and status bytes read from it.

Addresses for 8259As

8259A-1:FFF0H and FFF2H 8259A-2:FFF4H and FFF6H 8259A-3:FFF8H and FFFAH

Master and slave operation

1. Slave receives an interrupt signal on one of its IR inputs 2. Slave checks mask condition and priority of the interrupt request 3. If the interrupt is unmasked and its priority is higher than any other interrupt being serviced in the slave, the slave will send an INT signal to the IR input of a master

Master and slave operation

4. If that master IR input is unmasked and it has a higher priority than any other IR inputs currently being serviced, then the master will send an INT signal to the 8086 INTR input. 5. If the INTR interrupt is enabled, the 8086 will go through its interrupt procedure and sends out two INTA pulses to both master and the slave.

Master and slave operation

6. The slave ignores the first interrupt acknowledge pulse but the master outputs a 3-bit slave identification number on the CAS0-CAS1 lines to enable the slave. 7. When the slave receives the second INTA pulse from the 8086,the slave will send the desired interrupt type number to the 8086 an the eight data lines.

Master and slave operation

Note that; If an interrupt is applied directly to one of the IR inputs of the master, the master will send the desired interrupt type to the 8086 when it receives the second INTA pulse from the 8086.