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A low power digital device for electrical impedance measurements has been developed. It is
intended for embedded high precision sensor interface applications, but will also operate as a general
purpose phase sensitive detector. It integrates an automatic least mean square (LMS) AC bridge
with a digital dual phase lock-in amplifier, and is capable of measuring electrical impedance with
a precision of 0.001% (10ppm). Capacitance measurements with attofarad resolution have been
realized using the device.
Sensor DC input
impedance 90
deg.
Lock-In
channel 1
Reference Lock-In
impedance channel 2
In-phase
Error
balance
cancellation
algorithm Quadrature
balance
and the final lock-in amplifier output is This provides a very accurate method to track changes
in electrical impedance. If the sensor bridge is primarily
2vlowpass 1 z capacitive, Eq. 14 can conveniently be rewritten in terms
verr = = Zk ( + )A. (9)
A ZA ZB of capacitance as
In a real measurement situation Verr will contain broad- z2 − z1
CA = (verr − z0 )CB , (15)
band noise, DC offset etc., but such spurious components v2 − v1
are eliminated in the low pass filter stage leading to Eq. 9.
The error signal measured with the lock-in can be thus where CA = 1/iωZA and CB = 1/iωZB .
be expressed The equations given above rely on interpolation be-
tween two measurement points. Linear regression can
verr = Cz + D, (10) instead be used to determine C and D from a greater
number of measurements, thereby increasing the preci-
where C = Zk A/ZB and D = Zk A/ZA . The zero point sion of the method. The equations are easily modified to
balance ratio, z0 , fulfills allow for this.
Cz0 + D = 0. (11)
III. IMPLEMENTATION
The error cancellation algorithm will settle on a value
zauto close to z0 . We can then determine z0 with greater
The impedance detection scheme was implemented on
precision by measuring the lock-in error signal at two
an ARM based micro-controller using 32 bit integer arith-
settings of the balance near zauto , z1 = zauto − ∆z and
metics. Input and output signal were generated by 12 bit
z2 = zauto + ∆z:
DAC and ADC devices, and super-sampling used to pro-
v1 = Cz1 + D and v2 = Cz2 + D. (12) vide a theoretical 20bit balance ratio resolution. The
frequency range for the device was 10 Hz - 10 kHz,
These equations determine C and D through and the output signal amplitude was 0 - 4 V peak-to-
peak. The analog output stage consisted of two DC-
v2 − v1
C= , D = v1 − Cz1 , (13) coupled micro-power buffer amplifiers, while the input
z2 − z1 stage was a DC-coupled actively guarded ESD-protected
and with Eq. 11 we can therefore determine z0 = −D/C. micro-power operational amplifier with an low input bias
This leads to a significantly better approximation to the current of 200 fA. A 100 MΩ resistor to ground served as
zero balance point than zauto , due to the extreme se- the input bias current path. This input design was cho-
lectivity and noise suppression of the lock-in amplifier, sen to allow direct interfacing to a wide range of sensor
and the use of high signal amplification leading into the types. A secondary AC-coupled input amplifier with a
lock-in amplifier, made possible by the initial balancing fixed gain of 1,000 was used to amplify the error signal
performed by the error cancellation algorithm. leading into the dual phase lock-in amplifier.
Once the zero balance point z0 is determined, changes The use of micro-power devices throughout enabled the
in the relative impedance can be continuously derived entire device to operate from a single 5 V 150 mA supply,
from the lock-in error signal through: making it possible to power it directly from a standard
USB interface.
ZA C C z2 − z1 The device was controlled from a personal computer
= = = (verr − z0 )−1 . (14) via a serial (RS232) connection, and was able to operate
ZB D verr − Cz0 v2 − v1
3
0
V. CONCLUSIONS
-500 Im verr
∗
Electronic address: chris.p@sensawave.com Record, New York 4, 96 (1960).
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J. Vejdelek and S. Dado, Meas. Sci. Rev 3, 65 (2003).
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B. Widrow and M. E. Hoff, IRE WESCON Convention