University Of Hail Community College Electrical Engineering Department Electronics Engineering and Instrumentation Program Digital Circuits II (EEI

200)
Dr. Fawzy Hashem Date:

COUNTERS
ASYNCHRONOUS COUNTERS In an asynchronous counter, the clock is applied only to the first stage. Subsequent stages derive the clock from the previous stage. The three-bit asynchronous counter shown is typical. It uses three J-K flip-flops in the toggle mode.

Notice that the Q0 output is triggered on the leading edge of the clock signal. The following stage is triggered from Q0. The leading edge of Q0` is equivalent to the trailing edge of Q0. The resulting sequence is that of a 3-bit binary counter. Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. In following figure, notice how delays are cumulative as each stage in a counter is clocked later than the previous stage. The maximum clock frequency at which the counter can be operated is limited by the total cumulative propagation delay. For certain applications requiring high clock rates, this is a major disadvantage

ASYNCHROUNAS DECADE COUNTER This counter uses partial decoding to recycle the count sequence to zero after the 1001 state. The flip-flops are trailing-edge triggered, so clocks are derived from the Q outputs. Other truncated sequences can be obtained using a similar technique.

When Q1 and Q3 are HIGH together, the counter is cleared by a glitch on the CLR` line.

The 74LS93A ASYNCHRONOUS COUNTER The 74LS93A asynchronous counter has one independent toggle J-K flip-flop driven by CLK A and three toggle J-K flip-flops that form an asynchronous counter driven by CLK B. The counter can be extended to form a 4-bit counter by connecting Q0 to the CLK B input. Two inputs are provided that clear the count. All J and K inputs are connected internally to HIGH level.

The following figures show the 74LS93A asynchronous counter connected as modulus16 counter (by connecting Q0 to the CLK B input) and as a decade counter (by connecting Q1 and Q3 to the NANAD gate inputs).

SYNCHRONOUS COUNTERS In synchronous counter all flip-flops are clocked together with a common clock pulse. Synchronous counters overcome the disadvantage of accumulated propagation delays, but generally they require more circuitry to control states changes. A three bit synchronous counter logic diagram and its outputs waveform are shown below:

Notice that Q0 changes on each clock cycle, Q1 changes each time Q0 is HIGH (this change occurs at clocks 2, 4, 6, and8), Q2 changes each time both Q0 and Q1 are HIGH (this condition is detected by the AND gate and occurs at clocks 4 and 8) . DECADE SYNCHRONOUS COUNTERS: With some additional logic, a binary counter can be converted to a BCD synchronous decade counter. After reaching the count 1001, the counter recycles to 0000. An extra AND is used to detect state 1001, and causes FF3 to toggle on the next clock pulse. FF0 toggles on every clock pulse. Thus, the count starts over at 0000.

The timing waveforms of the decade synchronous counter Q0, Q1, Q2, and Q3 are shown below:

Notice that: Q0 : toggle on each clock ( J0 = K0 =1) Q1 : toggle on the next clock pulse each time Q0=1 & Q3=0 ( J1 = K1 = Q0 Q3`) Q2 : toggle on the next clock pulse each time both Q0=1 & Q1=1 ( J2 = K 2 = Q0 Q1) Q3 : toggle on the next clock pulse each time Q0=1 & Q1=1 & Q2 =1 (state 7) OR when both Q0=1 & Q3=1 (state 9) ( J3 = K3 = Q0 Q1 Q2 + Q0 Q3 )

THE 74LS163 SYNCHRONOUS COUNTER The 74LS163 is a 4-bit IC synchronous counter with additional features over a basic counter. It has parallel load, a CLR input, two chip enables, and a ripple count output (RCO) that signals when the count has reached the terminal (final) count.

The outputs waveforms of the 74LS163 4-bit IC synchronous counter show that: The LOW level pulse on the CLR` input causes all the outputs (Q0, Q1, Q2, and Q3) to go LOW (the counter is cleared). The LOW level pulse on the LOAD` input synchronously enters the data inputs (D0, D1, D2, and D3) into the counter (the counter is preset to state 12). The counter is then proceed through states 13,14, and 15 on the next three positive edge clock pulses and recycle back to state 0, 1, and 2. When the ENP goes LOW, the counter is inhibited (stop counting) and remains in the binary 2 state. Notice that both ENP and ENT inputs are HIGH during the state sequence.

UP/DOWN COUNTER An up/down counter is capable of progressing in either direction depending on a control input UP/DAWN`.

The timing waveforms of the UP/DOWN synchronous counter Q0, Q1, and Q2 are showing that: Q0 : toggle on each clock J0 = K0 = 1 Q1 : o for the UP sequence toggles on the next clock when Q0 =1 o for the DAWN sequence toggles on the next clock when Q0 =0 J1 = K1 = (Q0 . UP) + (Q0` . DOWN) Q2 : o for the UP sequence toggles on the next clock when Q0 = Q1= 1 o for the DAWN sequence toggles on the next clock when Q0 = Q1= 0 J2 = K2 = (Q0 . Q1 . UP) + (Q0`. Q1` . DOWN) THE 74HC190 SYNCHRONOUS UP/DOWN DECADE COUNTER

The 74HC190 is a high speed CMOS synchronous up/down decade counter with parallel load capability. It also has an active LOW ripple clock output (RCO) and a MAX/MIN output when the terminal count is reached.

CASCADED COUNTERS Cascading means that the last stage output of one counter drives the input stage of the next counter to achieving higher-modulus counters. The following figure shows two asynchronous cascaded counters with an overall modulus of 4x8= 32.

For synchronous IC counters, the next counter is enabled only when the terminal count (TC) of the previous stage is reached, as shown below:

Notice that: The terminal count (TC) of counter 1 is connected to the count enable (CTEN) input of counter 2. Thus counter 2 is inhibited by the LOW on its CTEN input until counter 1 reaches its last, or terminal, state (1001) and its terminal count output goes HIGH. 8

 This HIGH now enables counter 2, so that on the next clock pulse (CLK 10) counter 2 advances to its second state (from 0000 to 0001). Upon completion of the entire second cycle of counter 1, counter 2 is again enabled and advances to its next state (from 0001 to 0010). Thus for every ten cycles of counter 1, counter 2 goes through one cycle. This means that counter 2 will complete one cycle after the 100 clock pulse. The overall modulus of these two counters is 10x10=100.

DECODING COUNTERS Decoding is the detection of a binary number and can be done with an AND gate. A decoding counter which uses an AND gate to decode the decimal number 6 is shown below:

Notice that when Q0 = 0, Q1 = 1, Q2 = 1 a HIGH appears on the output of the decoding gate, indicating that the counter is at state 6. This is called active-HIGH decoding. Replacing the AND gate with a NAND gate provides active-LOW decoding. Another example of a decoding counter that detects state 2 and 7 using two three inputs AND gates is shown below:

COUNTER APPLICATIONS DIGITAL CLOCK The digital clock is a typical application of counters where synchronous divide-by-10 and divid-by-6 counters are utilized to provide the seconds, the minutes, and the hours counts.

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THE SECONDS AND MINUTES COUNTERS

Seconds and minutes counters count from 0 to 59 and then recycle back to 0. Notice that the divide-by-6 portion is formed with a decade counter with a truncated sequence achieved by using the decoder count 6 to asynchronously clear the counter. Also the terminal count 59 is decoded to enable the next counter in the chain.

THE HOURS COUNTER

The hours counter is implemented with a decade counter and a flip flop. Consider that initially both of them are RESET, and both the decode-9 gate and the decode-12 gate outputs are HIGH. 11

The decade counter advances through all of its state from 0 to 9, and on the clock pulse that recycles it from 9 back to 0 the flip flop goes to SET (J=1, K=0). This illuminates a 1 on the tens of hours display. The total count is now 10 (the decade counter in 0 state and the flip flop is SET). Next, the total count advances to 11 and then to 12. In the state 12 the Q2 output of the decade counter is HIGH, the flip flop is still SET, and thus the decode-12 gate output is LOW, this activates the LOAD` input of the decade counter. On the next clock pulse, the decade counter is preset to 0001 from the data inputs, and the flip flop is RESET (J=0, K=1). As you can see logic always cause the counter to recycle from 12 back to 1, rather than back to 0.

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