Digital System Design Half Adder

General Block Diagram: (Entity Level)

a h_adder b

Truth Table:

Inputs a 0 0 1 1 b 0 1 0 1 s

Outputs c

Detailed Block Diagram: (Architectural Level)

Department of Electronics Engg., P.V.P.I.T., Budhgaon

Digital System Design Half Adder

Experiment No: Title:

Date: ___ / ____ / __________

Theory:

Department of Electronics Engg., P.V.P.I.T., Budhgaon

Digital System Design Half Adder

EDA Tool Used: 1. PACKAGE USED: a. Device Family : b. Device :

c. Package Pins : d. Speed Grade : 2. Simulator: a. ISE Simulator b. Model-Sim Simulator 3. Synthesizer: a. XST synthesizer b. Leonardo Spectrum

Synthesis Report: 1. Hardware Inferred: (Names Only) a. _____________________________________ b. _____________________________________ c. _____________________________________ d. _____________________________________ e. _____________________________________ f. _____________________________________ 2. Device Utilization: a. Slices b. I/O Blocks c. Look Up Tables d. Flip Flops : ____ out of _______ ______ Percent : ____ out of _______ ______ Percent : ____ out of _______ ______ Percent : ____ out of _______ ______ Percent

Department of Electronics Engg., P.V.P.I.T., Budhgaon

Digital System Design Half Adder

Design Implementation Report: 1. Translation Report: Pins Description: Port Name a b s c 2. Mapping Report: a. Maximum Pad to Pad Delay : 3. Place and Route Report: a. Maximum Power Dissipation : b. Static Timing Report: Direction Pin Number

Department of Electronics Engg., P.V.P.I.T., Budhgaon