Classification of Digital Circuits

Combinational Logic
Basic element are Gates Circuit Behavior: Output depends on the present input Output depends only on present input. Examples: Comparator, Arithmetic Circuits

Sequential Logic
Basic elements are Flip Flops and Latches Further Classified into Synchronous and Asynchronous based on the clock. Circuit Behavior: Output depends on the past history. Examples: Counters, Shift Registers.

Sequential Logic Circuits

Sequential circuits primitive sequential elements combinational logic Models for representing sequential circuits finite-state machines (Moore and Mealy) representation of memory (states) changes in state (transitions) Basic sequential circuits shift registers counters Design procedure state diagrams state transition table next state functions

Combinational vs. Sequential Logic

Out

In

Combinational Logic Circuit

In

Out

Combinational Logic Circuit

State

Combinational Output = f(In)

Sequential

Output = f(In, Previous In)

Sequential Circuits

Sequential Circuits: Circuits require memory to store intermediate data, Sequential circuits use a periodic signal to determine when to store values. clock signal can determine storage times.Clock signals are periodic Single bit storage element is a flip flop A basic type of flip flop is a latch Latches are made from logic gates
NAND, NOR, AND, OR, Inverter
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Clock Pulse Definition

Positive Pulse

Negative Pulse

Positive Negative Edge Edge

Negative Positive Edge Edge

Edges can also be referred to as leading and trailing.

Sequential Circuits
Design steps

Sequential Circuits
Inputs Combinational circuit Next state Outputs Flip Flops

Present state

Timing signal (clock) Clock

a periodic external event (input) Clock

synchronizes when current state changes happen keeps system well-behaved makes it easier to design and build large systems

Latches and Flip-Flops

A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory The sequential devices differ in the way their outputs are changed:
The output of a latch changes independent of a clocking signal. The output of a flipflop changes at specific times determined by a clocking signal.

S-R Latch
SR latch based on NOR gates. The S input sets the Q output to 1 while R reset it to 0. When R=S=0 then the output keeps the previous value. When R=S=1 then Q=Q=0, and the latch may go to an unpredictable next state.

S-R Latch
SR latch based on NAND gates. The S input sets the Q output to 1 while R reset it to 0. When R=S=1 then the output keeps the previous value. When R=S=1 then Q=Q=1, and the latch may go to an unpredictable next state.

S-R Latch
The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAND gates. With NOR gates, the latch responds to active-HIGH inputs; with NAND gates, it responds to active-LOW inputs.

SR Latch Characteristics
0d 0 Excitation inputs S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Present state Q 0 1 0 1 0 1 0 1 (a) R (c) Next state Q* 0 1 0 0 1 1 No change SR Reset Set Not allowed Q 1 1 0 1 Q 0 00 0 01 0 11 01 (b) S 10 1 SR 10 1 d0

Q* = S + RQ

D Latch
This latch eliminates the problem that occurs in the SR latch when R=S=0. C is an enable input:
When C=1 then the output follows the input D and the latch is said to be open. When C=0 then the output retains its last value and the latch is said to be closed.

Flip-Flops
Flip-flops are synchronous bistable devices. The term synchronous means the output changes state only when the clock input is triggered, changes in the output occur in synchronization with the clock. An edge-triggered flip-flop changes states either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse on the control input. The three basic types are introduced here: S-R, J-K and D.

Flip-Flops
The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to the flipflop's output only on the triggering edge of the clock pulse. On the other hand, the direct set (SET) and clear (CLR) inputs are called asynchronous inputs, as they are inputs that affect the state of the flip-flop independent of the clock. For the synchronous operations to work properly, these asynchronous inputs must both be kept LOW.

D C

D flip-Flop
S
Q

D 0 1 X

1 1 0

Q 0 1 Q0

Q 1 0 Q0

Input value D is passed to output Q when Clock is high

Input value D is ignored when Clock is low

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D flip-Flop
CLK

Latches on following edge of clock

D
CLK

D Q

Q only changes when E is high

If CLK is high, Q will follow D

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D flip-Flop
CLK

Latches on following edge of clock

D
CLK

D Q

The D latch stores data indefinitely, regardless of input D values, if CLK = 0 Forms basic storage element in computers

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Characteristic Equations
algebraic descriptions of the next-state table of a flip-flop constructing from the Karnaugh map for Qt+1 in terms of the present state and input

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D Latch Characteristics
Enable input C 0 0 1 1 1 1 Excitation Present input state D 0 0 1 1 Q 0 1 0 1 0 1 (a) Next state Q* 0 1 0 0 1 1 Hold Store 0 Store 1 0d, 10 0 10 (b) CD 11 1 0d, 11

Q* = DC + CQ

With clk is high Q* = D

Symbols for Latches

SR latch is based on NOR gates SR latch based on NAND gates D latch can be based on either. D latch sometimes called delay latch

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D Flip-Flop
Stores a value on the positive edge of Clk Input changes at other times have no effect on output Positive edge triggered
D C Q Q

D 0 1 X

Q Q 0 1 1 0 0 Q0 Q0

D gets latched to Q on the rising edge of the clock.

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Master-Slave D Flip Flop

Consider two latches combined together Only one Clk value active at a time Output changes on falling edge of the clock

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Clocked D Flip-Flop
Stores a value on the positive edge of C Input changes at other times have no effect on output

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Edge Triggered J-K Flip-Flop

The operation of inputs J and K in the J-K flip-flop is similar to the operation of inputs S and R in the S-R flip-flop. The difference arises when J and K are asserted simultaneously. In this situation the output of the J-K flip-flop inverts its current state.

Edge Triggered J-K Flip-Flop

The J-K flip-flop is more versatile than the D flip flop. In addition to the clock input, it has two inputs, labeled J and K. When both J and K = 1, the output changes states (toggles) on the active clock edge (in this case, the rising edge).

Timing diagram for JK Flip-flop

Negative Edge Triggered

cloc k

Q
toggle J=K=1 hold J=K=0 reset J= 0 set J= 1

Clocked J-K Flip Flop

Two data inputs, J and K J -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table

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Characteristic equation of JKFF

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Master-slave JK flip-flop

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Edge Triggered J-K Flip-Flop

of the clock (for example the D or J-K inputs). Most flipflops have other inputs that are asynchronous, meaning they affect the output independent of the clock. Two such inputs are normally labeled preset (PRE) and clear (CLR). These inputs are usually active LOW. A J-K flip flop with active LOW preset and CLR is shown.

T Flip-Flop
Also known as the toggle flip-flop. When input T = 0 the output Q retain its previous value. When input T = 1 the output Q inverts on every tick of the clock. When inputs J and K of a J-K flip-flop are connected together, the J-K flip-flop will behave like a T flip-flop.

Positive Edge-Triggered T Flip-Flop

Created from D flop T=0 -> keep current K resets T=1 -> invert current

CL K

Q Q
Q Q

0 1

TOGGLE

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Asynchronous Inputs
J, K are synchronous inputs Effects on the output are synchronized with the CLK input. Asynchronous inputs operate independently of the synchronous inputs and clock Set the FF to 1/0 states at any time.

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Flip-flop Characteristics

Summary

Asynchronous sequential circuit

This is a system whose outputs depend upon the order in which its input variables change and can be affected at any instant of time. Gate-type asynchronous systems are basically combinational circuits with feedback paths. Because of the feedback among logic gates, the system may, at times, become unstable. Consequently they are not often used.

Synchronous sequential circuits

Synchronous sequential circuits use logic gates and flip-flop storage devices. Synchronization is achieved by a timing device called a clock pulse generator. Sequential circuits have a clock signal as one of their inputs. All state transitions in such circuits occur only when the clock value is either 0 or 1 or happen at the rising or falling edges of the clock depending on the type of memory elements used in the circuit. Clock pulses are distributed throughout the system in such a way that the flip-flops are affected only with the arrival of the synchronization pulse. Synchronous sequential circuits that use clock pulses in the inputs are called clocked-sequential circuits. They are stable and their timing can easily be broken down into independent discrete steps, each of which is considered separately.