UNIT 2

Addressing Modes and Instruction set

Objective:
To learn the different addressing modes To use commands for data movement, Arithmetic operations, Logical operations, Jump and Call instructions

Addressing modes
Introduction:
Data is stored at a source address and moved(copied) to a destination address. The ways by which these addresses are specified are called addressing modes.

Addressing modes of 8051:

Immediate Register Direct Register Indirect Indexed

Opcodes used to move Data (Data transfer instructions) are:

MOV MOVX MOVC PUSH and POP XCH

Instruction using #

Data

Immediate mode Instruction Using R0 to R7 Register R0 to R7 in Current Bank Register mode Instruction Using a RAM Address Source or Destination of Data

Address in RAM
Direct mode Instruction Using @R0 or @R1 Register R0 or R1 in Current Bank
Address in RAM

Source or Destination of Data

Address of Data

Source or Destination of Data Indexed mode

Immediate Addressing Mode:

The source operand is a constant The immediate data must be preceded by the pound sign ,#. This addressing mode can be used to load information into any of the registers, including the DPTR register. DPTR can be accessed as two 8-bit registers,DPH(high byte) and DPL(low byte) This addressing mode can be used to send data to 8051 ports.

Possible Mnemonics:
Mnemonic MOV Rr,#n

Operation Copy the 8 bit number into register Rr (of the current register bank)

Ex: MOV R0,#01h MOV R4,#65 MOV A,#n

Ex: MOV A,#0AAh

MOV DPTR,#nn

Put the immediate 8 bit no. 01h in register R0 Put the decimal value 65 in register R4 Copy the 8 bit number into the Accumulator register Put the immediate 8 bit no. AAh into the Accumulator register

Copy the 16 bit number nn into the DPTR register Ex:MOV DPTR,#1234h Put the immediate 16 bit no. 1234h into the DPTR register. It is the same as: MOV DPL,#34h (DPL :Low byte of DPTR) MOV DPH,#12h (DPH:High byte of DPTR)

Register Addressing Mode:

Register addressing mode involves the use of registers to hold the data to be manipulated. Movement of data between Rn registers is not allowed. Ex: MOV R0,R1 is invalid.

Possible Mnemonics:
MOV A,Rr Ex:MOV A,R5 Copy data from register Rr to register A Copy data from register Rr to register A

MOV Rr,A Ex:MOV A,R0

Copy data from register A to register Rr Copy data from R0 to register A

Direct Addressing Mode:

All 128 bytes of internal RAM and the SFRs may be addressed directly using the single byte addresses assigned to each RAM location and each special function register. Internal RAM uses addresses from 00h to 7Fh to address each byte. RAM locations 00-1FH : assigned to register banks and stack RAM locations 20-2FH : bit addressable space to save single bit data. RAM locations 30-7FH : place to save byte sized data.

The SFR addresses exist from 80h to FFh

Possible Mnemonics and related examples:

MOV A,addr Copy data from direct address addr to register A Copy data from port 0 pins to register A Copy data from register A to direct address addr

Ex: MOV A,80h

MOV addr,A

MOV Rr,addr

Copy data from direct address addr to Register Rr Ex:MOV R0,12h Copy data from RAM location 12h to Reg R0 MOV addr,Rr
Ex:MOV 8Ch,R7

Copy data from register Rr to direct address addr Copy data from register R7 to timer 0 high byte

MOV addr,#n

Copy immediate data byte n to direct address addr

Ex: MOV 3Ah,#3Ah Copy immediate data byte 3Ah to RAM location 3Ah MOV addr1,addr2 Copy data from direct address aadr2 to direct address addr1 Ex: MOV 0A8h,77h Copy data from RAM location 77h to IE register

Indirect Addressing Mode:

The indirect addressing mode uses a register to hold the actual address that will finally be used in the data move. Only registers R0 and R1 (called as data pointers) are used to hold the address of one of the data locations in RAM from address 00h to 7Fh. The mnemonic symbol used for indirect addressing is the at sign, @.

Possible Mnemonics and related examples:

MOV @Rp,#n MOV @Rp,addr MOV @Rp,A Ex: MOV A,#55h MOV R0,#40h Copy the immediate byte n to the address in Rp Copy the content of addr to the address in Rp Copy the data in A to the address in Rp

MOV @R0,A MOV addr,@Rp MOV A,@Rp Ex: MOV A,@R1

Copy 55h to RAM location R0 points to (i.e.RAM location 40h). Copy the contents of the address in Rp to addr Copy the contents of the address in Rp to A

Indexed addressing mode and on-chip ROM access:

Indexed addressing mode is widely used in accessing data elements of look-up table entries located in the program ROM space of the 8051. Instruction used: MOVC A,@A+DPTR Copy the code byte, found at the ROM address formed by adding A and the DPTR, to A Letter C is added to the MOV mnemonic to highlight the use of

the opcodes for moving the data from the source address in the code ROM address. MOVC A,@A+PC Copy the code byte, found at the ROM address formed by adding A and the PC, to A

What is the end result of the following program segments? 1.MOV DPTR,#1234H MOV A,#56H MOVC A,@A+DPTR

2.MOVC A,@A+PC if PC contains 4000h and A contains 58h when the opcode is executed

Note:PC is incremented by 1 before it is added to A to form the final address of the code byte Hence code address is:4059h

External Data Moves:

It is possible to expand RAM and ROM memory space by adding external memory chips to the 8051 microcontroller. External memory can be as large as 64K for each of the RAM and ROM memory areas. Indirect addressing is used to specify the external memory. The registers used are:R0,R1 and DPTR R0 and R1 are limited to external RAM address ranges of 00h to 0FFh, and DPTR can address the maximum RAM space of 0000h to 0FFFFh. Letter X is added to the MOV mnemonic to indicate that the data move is external to the 8051.

8051
Read Write
A register

Data Bus
Read Write Data External RAM Data Internal and External ROM Read

Addressing Instruction
MOVX @Rp

R0 or R1

DPTR
DPTR+A

MOVX @DPTR MOVC A,@A+DPTR

PC+A

MOVC A,@A+PC

External Addressing using MOVX and MOVC

PUSH and POP Opcodes:

The data moves between an area of internal RAM, known as stack, and the specified address. SP contains the address in RAM where the data from the source address will be PUSHed or where data has to be POPed to the destination address is found. In the instruction, it is implied that the SP holds the indirect address during PUSH and POP. The SP register is set to 07h(direct address in internal RAM as register R7 in bank 0) when the 8051 is reset. SP SP-1 SP-2
Decrement After POPing

SP+2 Push Y SP+1 SP Push X

Y X

Increment before PUSHing

Internal

PUSH Opcode:

Copies data from source address to the stack SP is incremented by 1 before the data is copied to the internal RAM location contained in SP so that the data is stored from low address to high addresses in the internal RAM.

POP Opcode:

Copies data from the stack to the destination address. SP is decremented by 1 after data is copied from the stack RAM address to the direct destination to ensure that data placed on the stack is retrieved in the same order as it was stored.

Mnemonic:
PUSH addr POP addr

Increment SP;copy the data in addr to the internal RAM address contained in SP. Copy the data from the internal RAM address contained in SP to addr; decrement

Examples of PUSH and POP opcodes:

MOV 81h,#30h MOV R0,#0ACh PUSH 00h PUSH 00h POP 01h POP 80h copy immediate data 30h to the sp copy the immediate data ACh to R0 SP=31h;address 31h contains the number ACh SP=32h;address 32h contains the number ACh SP=31h;register R1 now contains the number ACh SP=30h;port 0 latch now contains the number Ach

Note:Direct addresses for R0-R7 must be used, not register names.

Data Exchanges:

Exchange instructions actually move data in two directions: From source to destination and from destination to source. Immediate addressing modes may not be used in the XCH(exchange) instructions

Mnemonics:

XCH A,Rr Exchange data bytes between register Rr and A Eg:XCH A,R7 XCH A,addr Exchange data bytes between addr and A Eg:XCH A,0F0h XCH A,@Rp Exchange data bytes between A and address in Rp Ex:XCH A,@R1 XCHD A,@Rp Exchange lower nibble between A and address in Rp. Ex:XCHD A,@R1 Exchange lower nibble in A and the address in R1.

Example programs:
1.Swap the contents of registers R7 and R6 in register bank 0. Method 1: MOV A,R6 MOV R5,A MOV A,R7 MOV R6,A MOV A,R5 MOV R7,A Method 2: MOV 10H,06H MOV 06H,07H MOV 07H,10H Copy the contents of R6 to RAM address 10h Copy the contents of R7 to R6 Copy the saved contents of R6 to R7

Method 3:
PUSH 07H PUSH 06H POP 07H POP 06H
Method 4: XCH A,R6 XCH A,R7 XCH A,R6 Exchange contents of A and R6 Contents of R6 now in R7;R7 in A Contents of R7 now in R6

2.Write a program to rotate the bytes in registers R0 to R3:copy the data in R0 to R1,R1 to R2,R2 to R3,and R3 to R0
CLR A XCH A,R0 XCH A,R1 XCH A,R1 XCH A,R2 XCH A,R2 XCH A,R3

3.WAP to get the x value from P1 and send x2 to P2, continuously ORG 0 MOV DPTR,#300H ;look-up table address loaded ;to DPTR ;Configure P1 as input port

MOV A,#0FFH MOV P1,A BACK:MOV A,P1 ;Get x through P1 MOVC A,@A+DPTR ;Get x2 from table MOV P2,A ;send it to P2 SJMP BACK ;repeat the process ORG 300H XSQR_TBLE: DB 0,1,4,9,16,25,36,49,64,81 END

Arithmetic instructions Objectives:

Use instructions to increment and decrement the contents of registers and RAM Perform signed and unsigned addition and subtraction Perform unsigned multiplication and division Perform BCD addition

There are 24 arithmetic opcodes that are grouped into the following types: INC destination ; Increment destination by 1 DEC destination ; Decrement destination by 1 ADD/ADDC destination, source ;ADD source to destination ;without/with Carry flag SUBB destination, source ;Subtract, with Carry, source ;from destination MUL AB ;Multiply the contents of ;registers A and B DIV AB ;Divide the contents of registers A by the contents of register B DA A ;Decimal Adjust the A register.

The 8051 has several dedicated latches,or flags,that store results of arithmetic operation. The four arithmetic flags of 8051 are: Carry ,Auxiliary carry(AC),Overflow(OV),and Parity(P). The C,AC and OV flags are either set to 1 or cleared to 0 automatically, depending on the instructions. The flags are all stored in the PSW. The Parity flag is affected by every instruction executed.The P flag will be set to a 1 if the number of 1s in the A register is odd and will be set to 0 if the number of 1s is even. Parity check is an elementary error checking method and is particularly valuable when checking data received via the serial port.

Incrementing and Decrementing

INC(Increment) and and DEC(decrement) operations involve adding or subtracting a binary 1 and a number. No math flags(C,AC,OV) are affected. Mnemonics: INC A Add a 1 to the A register INC Rr Add a 1 to the Rr register INC addr Add a 1 to contents of the direct memory address. INC @Rp Add a 1 to the contents of the memory address in Rp INC DPTR Add a 1 to the 16bit DPTR

DEC A DEC Rr DEC add

DEC @Rp

Subtract a 1 from Subtract a 1 from Subtract a 1 from memory address. Subtract a 1 from address in Rp

register A register Rr contents of the direct

the contents of the memory

Ex1: MOV R0,#15h MOV 15H,#12H INC @R0 DEC 15H Ex2:MOV DPTR,#12FFh INC DPTR DEC 83h

R0=15h Internal RAM address 15H=12H Internal RAM address 15H=13H Internal RAM address 15H=12H DPTR=12FFh DPTR=1300h DPTR=1200h(SFR 83h is the DPh byte)

Addition:

All addition is done with the A register as the destination of the result. Carry flag is set to 1 if there is a carry out of bit position 7;it is cleared to 0 otherwise. The OV flag is set to 1 if there is a carry out of bit position 7,but not bit position 6 or if there is a carry out of bit position 6 but not bit position 7. This may be expressed as the logical operation: OV=C7 XOR C6

Unsigned and Signed Addition:

Unsigned addition:
The numbers that are 8 bit positive binary numbers ranging from 00h to FFh. Carry flag is used to detect when the result of an ADD operation is a number larger that FFh. The OV flag is not used for unsigned addition and subtraction.

Ex; 95d = 01011111b 189d = 10111101b ________ _________ 284d =100011100b

= 5Fh =BDh _____ 1)1Ch

carry flag is set to 1

Signed Addition:
Signed numbers use bit 7 as a sign bit in the Most Significant Byte of the number. Bits 0 to 6 of the MSB and any other bytes, express the magnitude of the number. Signed numbers use a 1 in bit position 7 of the MSB as a negative sign and a 0 as a positive sign. The negative numbers are in twos complement form. In signed form,a single byte number may range in size from 10000000b(=-128d) to 01111111b(=+127d).

Addition of Unlike Signed numbers:

The result cannot be greater than -128d or +127d and the sign of the result will always be correct.

-001d = 11111111b +027d = 00011011b ______ __________ +026d 1)00011010b

=FFh =1Bh ____ 1)1Ah

There is a carry from bit 7,hence carry flag is 1. There is also a carry from bit 6,and OV flag is 0. For this condition, no action need be taken by the program to correct the sum.

Addition of like signed numbers: Ex: Addition of two positive numbers where the result exceeds +127d

+100d = 01100100b +050d = 00110010b ______ ____________ +150d =1)10010110b

= 64h = 32h _____ =0)96h

There is no carry from bit 7 and the Carry flag is 0 and there is a carry from bit 6 so the OV flag is 1.
Ex: Addition of two positive numbers where the result does not exceed +127d +045d = 00101101b =2Dh +075d = 01001011b =4Bh ______ ____________ _____ +120d 0)01111000b 0)78h
No carries from bits 6 or 7 of sum and Carry,OV flags are both 0.

Ex: Addition of two negative numbers where the result does not exceed the ve limit -030d -050d _____ -080d = = 11100010b 11001110b ____________ 1)10110000b = E2h = CEh _____ 1)B0h

There is a carry from bit 7 and the Carry flag is 1; There is a carry from bit 6 and the OV flag is 0. No corrections are needed for the sum. Ex: Addition of two negative numbers where the result exceeds the ve limit(-128d)

-070d = 10111010b -070d = 10111010b ______ ____________ -140d 1) 01110100b= +116d

= BAh = BAh _______ 1)74h

There is a carry from bit position 7, and no carry from bit position 6, so the Carry and the OV flags are set to 1.
The programming actions needed for the C and OV flags are: Flags C OV 0 0 0 1 1 0 1 1 Action None Complement the sign None Complement the sign

The OV flag also indicates that the sum exceeds the largest positive or negative numbers range.

Addition mnemonics
ADD A,#n Add A and the immediate number n;put the sum in A Add A ,immediate number n and the C flag;put the sum in A Add A and register Rr;sum in A Add A,register Rr and C flag;sum in A

ADDC A,#n
ADD A,Rr ADDC A,Rr ADD A,addr ADDC A,addr

Add A and the address contents;sum in A Add A ,address contents and the C flag;sum in A ADD A,@Rp Add A and the contents of the address in Rp;sum in A ADDC A,@Rp Add A, contents of the address in Rp and C flag;sum in A

Eg 1:Addition of two 8 bit numbers stored in registers R0 and R1.Verify if their sum is greater than FFh. MOV A,R0 ADD A,R1 JC yes SJMP next yes: MOV A,FFh Next: NOP END

Eg 2:WAP to add two 16 bit numbers ;This program adds two 16 bit no.s stored in 20h(ls byte),21h(ms byte) and ;30h(ls byte),31h(ms byte) ;ls bytes of both the locations are added and the result is stored in 40h ,ms bytes along ;with carry generated are added and the result is stored in 41h,carry generated is stored in ;42h org 0h start: mov r0,#20h ;r0 pointing to lsb of src1 mov r1,#30h ;r1 pointing to lsb of src2 mov a,@r0 ;add lsb of src1 and src2 add a,@r1 mov 40h,a ;result stored at 40h inc r0 ;r0 pointing to msb of src1 inc r1 ;r0 pointing to msb of src2

mov a,@r0 addc a,@r1 mov 41h,a mov a,#0h addc a,#0h mov 42h,a sjmp start end

;add msb of src1 and src2 with ;carry ;result stored at 41h
;carry stored at 42h

8051 has commands to perform direct subtraction of two signed or unsigned numbers. Register A is the destination address for subtraction. Carry flag is treated as a borrow and always the carry flag is subtracted as a part of the operation. C flag is set if a borrow is needed into bit 7 and reset otherwise. AC flag is set if there is a borrow needed into bit 3 and reset otherwise. OV flag is set if there is a borrow into bit 7 and not bit 6 or if there is a borrow into bit 6 and not bit 7. The OV flag is the XOR of the borrows into bit positions 7 and 6.

Subtraction

Mnemonics:
SUBB A,#n SUBB A,addr

;subtract immediate number n and the ;carry flag C from A;put the result in A ;subtract the contents of addr and the C ;flag from A;put the result in A

SUBB A,Rr SUBB A,@Rp

;subtract Rr and C flag from A;put the ;result in A ;subtract the contents of the address in Rp ;and the C flag from A;put the result in A

Unsigned Subtraction:
Initially C flag should be cleared. The result will be in true form, with no borrow if the source number is smaller than A, or in twos complement form with a borrow if the source is larger than A. Eg 1: subtraction of a larger number from a smaller number

015d = 00001111b SUBB 100d = 01100100b __________ _________________ -085d = 1)10101011b=171d

= 0Fh = 64h ______ =1)Abh

C flag:set to 1;OV flag set to 0;Twos complement of result:085d

Eg 2: subtraction of a smaller number from a larger number 100d = 01100100b = 64h = 0Fh ______ =0)55h

SUBB 015d = 00001111b __________ _________________ 085d = 0)01010101b=085d

C flag:set to 0;OV flag set to 0;Magnitude of the result is in true form.

Signed subtraction: Subtraction of like Signed numbers: Result does not exceed the positive or negative magnitude limits of +127d or -128d.So, the magnitude and the sign of the result do not need to be adjusted.

Eg 1: +100d= 01100100b +126d= 01111110b _________ ___________ -026d 1)11100110b=-026d

= 64h = 7Eh ________ =1)E6h

There is a borrow into bit position 7 and 6. Carry flag is set to 1 OV flag is cleared.
Eg 2: -061d= -116d= ________ +055d 11000011b 10001100b _______________ 0)00110111b =+55d =C3h =8Ch ______ 0)37h

No borrows into bit positions 6 or 7 Carry and OV flags are cleared to 0.

Subtraction of unlike Signed numbers:

An overflow may be possible. Eg 1: -099d = 10011101b = 9Dh +100d = 01100100b = 64h ________ _____________ _______ -199d 0)00111001b=+057d 039h There is a borrow into bit position 6; OV flag is set to 1;Hence result must be adjusted. No borrow into bit position 7;Carry flag is cleared to 0. Eg 2:+087d = 01010111b =57h -052d = 11001100b =CCh ________ ___________ _______ +139d 1)10001011b=-117d 1)8Bh Both OV and Carry flag are set to 1;Since OV flag is set, answer must be adjusted.

The general rule is that: if the OV flag is set to 1,then complement the sign bit. OV flag also signals that the result is greater than -128d or +127d. Example program:
Eg1: Find the result available in the accumulator: CLR C MOV A,#3Fh MOV R3,#23h SUBB A,R3 Solution: A = 3F 0011 1111 R3= 23 0010 0011 ____ 1C 0011 1111 + 1101 1101(2s complement) ___________ 1 0001 1100 0 CF=0 CY=0,AC=0 and carry flag must be checked to determine if the result is positive or negative.

Eg 2:WAP to subtract two 16 bit numbers ;This program subtracts two 16 bit no.s stored in 20h(ls byte),21h(ms byte) and ;30h(ls byte),31h(ms byte) ;ls byte in 30h is subtracted from ls byte in 20h and the result is stored in 40h ,ms byte in ;31h is subtracted from ms byte in 21h along with borrow and the result is stored in 41h // program to subtract two 16 bit numbers //result available in 40h and 41h(40 lsb;41 msb) org 0h here: clr c ;clear carry bit mov r0,#20h ;r0 pointing to lsb of src1 mov r1,#30h ;r1 pointing to lsb of src2 mov a,@r0 ;sub lsb of src2 from lsb of src1 subb a,@r1 mov 40h,a ;result stored at 40h inc r0 ;r0 pointing to msb of src1 inc r1 ;r0 pointing to msb of src2 mov a,@r0 subb a,@r1 ;sub msbs with borrow mov 41h,a ;result stored at 41h sjmp here end

Multiplication and Division:

8 bit integer multiplication and division can be performed using the A and B registers. Register A holds 1 byte of data before a multiply or division operation, and one of the result bytes after a multiply or divide operation. The numbers in A and B are treated as unsigned numbers. Multiplication: The unsigned number in Reg. A is mutiplied by the unsigned number in Reg.B MUL AB ;Multiply A by B;put the low order byte of the product in A and high order product in B OV flag will be set if AB>FFh.It does not imply that the result is wrong. It signals that the result is larger than 8 bits and the higher byte of the result is available in B register. Carry flag is always cleared to 0.

Eg 1:WAP to find the square of the number in the range 0h to ffh ;This program finds the square of the number in data RAM 20h ;and stores the square in 30h and 31h ;the no. is stored in acc and b reg org 0h mov r0,#20H mov a,@r0 ;num in 20h is loaded into acc and b reg. mov 0f0h,a mul ab mov 030h,a ;lower order product in 30h mov 031h,0f0h ;higher order product in 31h here: sjmp here end

Division:
DIV AB

The unsigned number in A is divided by unsigned number in B

Divide A by B;put the integer part of the quotient in register A and the integer part of the remainder in B

OV flag is set to 1 if division by 0 occurs. Carry flag is always reset.

Eg 1: In a semester, a student has to take six course. The marks of the student(out of 25) are stored in RAM locations 47H onwards. Find the average marks and output it on port 1. MOV R1,#06H MOV B,#06 MOV R0,#47h MOV A,#0 ADD A,@R0 INC R0 DJNZ R1,BACK ;R1:No. of courses ; B:No. of courses ;R0:pointer to data ;Clear A ;Sum stored at A ;R0 points to next location ;repeat addition until R1=0

DIV AB MOV P1,A

;Divide sum by 6 to get the average(quotient) in reg A ;send the average to port1.

Logical instructions
The logical operations can be at two data levels: byte or bit

Byte Level Logical Operations: The entire byte is affected with the operation

The A register or a direct address in internal RAM is the destination of the logical operation result.

ANL A,#n
ANL

ANL
ANL ANL ANL

;AND each bit of A with the same bit of immediate number n;put the result in A A,addr ;AND each bit of A with the same bit of direct RAM address;put the result in A A,Rr ;AND each bit of A with the same bit of Rr;put the result in A A,@Rp ;Guess? addr,A ; Guess? addr,#n ;Guess?

Eg: MOV A,#0FFh MOV R0,#77h ANL A,R0 Output? ORL A,#n ORL ORL ORL ORL ORL ;OR each bit of A with the same bit of n;put the ;result in A A,addr ;Guess? A,Rr ; A,@Rp ; addr,A ; addr,#n ;

Eg: MOV A,#0FFh MOV R0,#77h ORL A,R0

Output?

XRL A,#n XRL XRL XRL XRL XRL

;XOR each bit of A with the same bit of n;put the ;result in A A,addr ; A,Rr A,@Rp addr,A addr,#n

Eg: MOV A,#0FFh MOV R0,#77h XRL A,R0 Output? CLR A CPL A ;Clear each bit of A register to 0 ;Complement each bit of A; each 1 becomes a 0 ;and each 0 becomes a 1 Eg: MOV A,#00H CPL A
Output?

No flags are affected by the byte level logical operations unless the direct address is the PSW. Bit Level Logical Operations: An area of RAM contains data addresses that hold a single bit. Internal RAM byte addresses 20h to 2Fh are both byte and bit addressable. The bit addresses are numbered from 00h to 7Fh to represent the 128d bit addresses(16d bytes X 8 bits) that exist from byte addresses 20h to 2Fh. Bit 0 of byte address 20h is bit address 00h, and bit 7 of byte address 2Fh is bit address 7Fh.

Internal RAM Bit Addresses

The correspondence between byte and bit addresses is shown in the table below:

Bit Addressable Memory

2F
2E 2D 2C 2B 2A 29

7F

78

28
27 26

25
24 23 22
0F 07 06 05 04 03 02 01 1A 10 08 00

21
20

SFR Bit Addresses:

All SFRs may be addressed at the byte level by using the direct address assigned to it, but not all of the SFRs are addressable at the bit level. The SFRs that are also bit addressable form the bit address by using the five most significant bits of the direct address for that SFR, together with the three least significant bits that identify the bit position from position 0(LSB) to 7(MSB) The bit addressable SFR and the corresponding bit addresses are already discussed.

Bit addressable SFRs and the function of each addressable bit is shown in the following table.
SFRs and their addresses from unit 1.

Bit Level Boolean Operations Bit level Boolean logical opcodes operate on any addressable RAM or SFR bit. The Carry flag in the PSW special function register is the destination for most of the opcodes. C flag either sets or resets depending on the operation. ANL C,b ANL C,/b ORL C,b ORL C,/b CPL C CPL b CLR C AND C and the addressed bit; put the result in C AND C and the complement of the addressed bit; put the result in C; the addressed bit is not altered. OR C and the addressed bit; put the result in C OR C and the complement of the addressed bit; put the result in C; the addressed bit is not altered. Complement the C flag Complement the addressed bit Clear the C flag to 0

CLR b MOV C,b MOV b,C SETB C SETB b

Clear the addressed bit to 0. Copy the addressed bit to the C flag. Copy the C flag to the addressed bit. Set the C flag to 1 Set the addressed bit to 1

The bit instructions that can use a SFR latch bit are: CLR, CPL, MOV and SETB. Eg: SETB 00h MOV C,00h MOV 7Fh,C Bit 0 of bit addressable RAM byte 20h=1 C=1 Bit 7 of RAM byte 2Fh=1

Rotate and Swap Operations

The A register can be rotated one bit position to the left or right with or without including the C flag in the rotation. If the C flag is not included, then the rotation involves the eight bits of the A registers, if included, it involves nine bits. Including the C flag enables the programmer to construct the rotate operations involving any number of bytes. SWAP instruction can be thought of as a rotation of nibbles in the A register.

RL A

RLC

TRY for RR A , RRC A and SWAP A instructions ?

RL A RLC A

Rotate the A register one bit position to the left. Rotate the A register along with Carry one bit position to the left RR A Rotate the A register one bit position to the right. RRC A Rotate the A register along with Carry one bit position to the right SWAP A Interchange the nibbles of register A; put the high nibble in the low nibble position and the low nibble in the high nibble position No other flags, other than the Carry flag in RRC and RLC are affected. Eg: 1.Swap every even numbered bit of register R3 in bank 0 with the odd numbered bit to its left. Swap bit 0 with bit 1,bit 2 with bit 3,......bit 6 with bit 7. MOV A,R3 RL A

ANL A,#0AAh PUSH ACC MOV A,R3 RR A ANL A,#055h MOV R3,A POP ACC ORL 03h,A

2.Write a program that will swap the bits of each nibble in register R5. Swap bits 0 and 1 with bits 2 and 3, and bits 4 and 5 with bits 6 and 7.

Jump and Call Instructions

The jumps and call codes are decision codes that alter the flow of the program by examining the results of the action codes and changing the contents of the program counter. A jump permanently changes the contents of the program counter if certain program conditions exist. A call temporarily changes the program counter to allow another part of the program to run. Jumps and Calls may also be generally referred to as branches, which emphasizes that two divergent paths are made possible by this type of instruction.

The Jump and Call program Range

The difference, in bytes, of the new address from the address in the program where the jump or call is located is called the range of the jump or call.

Jump or Call instructions may have one of the three ranges:

Relative range: +128d,-128d bytes from the instruction following the jump or call instruction. Absolute range: on the same 2K byte page as the instruction following the jump or call Long range: any address from 0000h to FFFFh, anywhere in program memory

Relative Range: Jumps that replace the PC contents with a new address that is greater than the address of the instruction following the jump by -127d or less than the address of the instruction following the jump by 128d are called relative jumps. Short Absolute Range: Absolute jump makes use of the concept of dividing memory into logical divisions called pages. 8051 program memory is arranged as 2K pages, giving a total of 32d(20h) pages.Hexadecimal address of each page is shown below:

Fig. 8.1( Ayala )

Table 8.1( Ayala)

Page 00 01 02

Address(Hex) 0000-07FF 0800-0FFF 1000-17FF

Absolute addressing has the advantage of allowing jumps or calls over longer programming distances than does relative addressing.

Long Absolute Range:Addresses that can access the entire

program spae from 0000h to FFFFh use long-range addressing. It is more likely to be used in large programs.

Jumps:The 8051 has a rich set of jumps that can operate at the bit

and byte levels. Jumps operate by testing for conditions that are specified in the jump mnemonic. If Condition is true: the PC is altered to the address that is part of the jump instruction. If Condition is false: instruction immediately following the jump instruction is executed. Bit Jumps:operate according to the status of the Carry flag in the PSW or the status of any bit-addressable location. All bit jumps are relative to the program counter.

JC radd JNC radd JB b,radd JNB b,radd JBC b,radd

Jump relative if the Carry flag is set to 1 Jump relative if addressable bit is set to 1 Jump relative if addressable bit is set, and clear the addressable bit to 0.

Eg:WAP to multiply two 8 bit numbers. Use the technique of repeated addition. mov r1,#0 mov a,#0 mov r0,#25h Again: add a,#0ECh jnc here inc r1 Here: djnz r0,again mov r0,a ;register to store MSB ;multiplier placed in r0 ;multiplicand to accumulator ;if no carry, then repeat addition ;increment r1 for each carry generated ;repeat until r0=0 ;lsb of product is moved to r0,msb of the ;product is in r1;r1=22h and r0=1Ch.

Byte Jumps: jump instructions that tests bytes of data. If the condition that is tested is true, the jump is taken. If the condition is false, the instruction after jump is executed. All byte jumps are relative to the program counter.
CJNE A,add,radd Compare the contents of the A register with the contents of the direct address;if they are not equal,then jump to the relative address;set the carry flag to 1 if A<contents of direct address. CJNE A,#n,radd Similar to the above instruction CJNE Rr,#n,radd CJNE @Rp,#n,radd DJNZ Rr,radd ;no flags are affectd DJNZ add,radd ;Decrement the direct address by 1 and jump to the relative address if the result is not zero;no flags are affected unless the direct address is the PSW. JZ radd ;Jump to the relative address if A is 0;the flags and A contents are not changed. JNZ radd

Unconditional Jumps: They do not test any bit or byte to determine whether the jump should be taken. All jump ranges are found in this group of jumps as the jump can be to any location in memory. JMP @A+DPTR ;Jump to the address formed by adding A to the DPTR;the address can be anywhere in the program memory;A,DPTR and the flags are unchanged. AJMP sadd ;Jump to absolute short range address sadd;no flags are affected LJMP ladd ;Jump to absolute long range address ladd;no flags are affected. SJMP radd ;Jump to relative address radd;no flags affected. NOP(no operation) ;Do nothing and go to the next instruction;used in a software timing loop;no flags affected.

Eg.2:WAP to sort an array stored in the internal RAM using subroutine instructions ;This program arranges elements in ascending order in a given ;array in the internal RAM ;5 elements are stored from location 50h ;r0 and r1 are used as data pointers;r2 and r3 are used as ;counters,to keep track of the no. of comparisons in each pass ;and the no. of pass respectively. ;two consecutive elements are compared. If the I element is ;greater than the II element, then the two elements are ;exchanged. org 0000h num equ 040h mov r3,#04h back1: mov r0,#50h mov a,r0 mov r1,a

;store n elements(say n=5) from 50h ;r0 and r1 are used as pointers

mov a,r3 mov r2,a back: mov a,@r0 inc r1 mov num,@r1 cjne a,num,loop sjmp next jc next

;load (n-1) to r3 (no. of passes) ;load r3 to r2(no. of comparison in each pass) ;compare no. pointed to by r0 with no. ;pointed to by r1

loop:

//jnc next for descending order acall exchg ;else call the subroutine to exchange the ;two numbers next: inc r0 djnz r2,back ;decrement no. of comparison djnz r3,back1 ;decrement no. of passes

;if num at r0<no. at r1 continue with ;comparison process

here: sjmp here exchg: mov r4,a mov a,@r1 mov @r0,a mov a,r4 mov @r1,a ret end