Memory Management

Managing processes in the main memory and moving data in and out to/from secondary memory
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Responsibilities
Organization of main memory Allocation of memory to processes Dynamic relocation Sharing Protection

Memory Management
Ideally programmers want memory that is
large fast non volatile

Memory hierarchy
small amount of fast, expensive memory cache some medium-speed, medium price main memory gigabytes of slow, cheap disk storage Memory manager handles the memory hierarchy
3

Aims
Access time small Size Large Cost effective => Design Constraints Wasted memory Time complexity Memory access overhead

Initial approaches
Dynamic loading Dynamic linking / Shared libraries Overlays / Swapping

Memory Management policies

Contiguous memory allocation policy
Single contiguous
Static partitioning Dynamic Partitioning

Non-Contiguous allocation policy

Paging Segmentation

Virtual Memory
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Monoprogramming
0xFFFF
Operating system (ROM) Device drivers (ROM) User program (RAM) Operating system (RAM)

User program (RAM)

Operating system (RAM)

User program (RAM)

Monoprogramming
Simple, no special hardware, no address translation Problems :
Poor CPU utilization in presence of I/O waiting Poor memory utilization with many processes Processes must fit into memory

Idea
Subdivide memory and run more than one process at once!!!! Multiprogramming, Multitasking

How to divide ? .. Approach 1

Fixed partition contiguous allocation Divide memory into fixed equal-sized partitions Any process <= partition size can be loaded into any partition

Wasted space, Jobs must fit in partitions

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Fixed partition contiguous allocation

Any unused space in the partition is wasted Called internal fragmentation Processes smaller than main memory, but larger than a partition cannot run.
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Fixed variable-sized partitions(1)

Multiple queues Place process in queue for smallest partition that it fits in. Small jobs available, but only large partition free Some partitions may be idle
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900K Partition 4 Partition 3 Partition 2 Partition 1 OS 700K 600K 500K

100K
0

Fixed variable-sized partitions(2)

Single queue, search for any job that fits Small jobs in large partition if necessary
900K Partition 4 Partition 3 Partition 2 Partition 1 700K 600K 500K

Process
OS

100K

Increases internal fragmentation 0

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How many processes are enough?

Several memory partitions (fixed or variable size) Lots of processes wanting to use the CPU Tradeoff
More processes utilize CPU better Fewer processes use less memory (cheaper!)

How many processes do we need to keep the CPU fully utilized? This will help determine how much memory we need
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Fixed Partition Summary

Simple and Easy to implement Poor memory utilization Internal fragmentation Limited no. of active processes Used on OS/360 operating system (OS/MFT) Still applicable in some simple embedded systems
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How to divide ? .. Approach 2

Dynamic Partitioning Partitions are of variable length Process is allocated exactly what it needs
Assume a process knows what it needs

Also called Swapping

Processes swapped in and out

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Dynamic Partitioning
B A OS

A OS

C B A
OS

C B
OS

C B
D OS

C
D OS

C
A D OS

Memory allocation changes as

Processes come into memory Processes leave memory Swapped to disk Complete execution
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Leaving room to grow

Need to allow for programs to grow
Allocate more memory for data Larger stack Process B Stack Room for B to grow Data

Handled by allocating more space than is necessary at the start

Inefficient: wastes memory thats not currently in use What if the process requests too much memory? Process A

Code Stack
Room for A to grow

Data
Code OS
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Unresolved problems
1. Entire program in main memory 2. Maximum size < Physical memory size 3. Contiguous store Solutions 1 & 2 -> Secondary memory --logical extension of main memory 3 -> Map virtual address to discontinuous store
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Virtual Memory
Problems:
Programs too big for main memory; Large programs limit degree of multiprogramming

Solution:
Keep only those parts of the programs in main memory that are currently in use

Basic idea:
A map between program-generated addresses (virtual address space) and main memory

Main techniques: paging and segmentation

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Virtual and physical addresses

Program uses virtual addresses
Addresses local to the process H/w translates virtual address to physical address CPU
Virtual addresses from CPU to MMU

CPU chip
MMU

Translation done by Memory Management Unit

the
Physical addresses on bus, in memory

Memory

Usually on the same chip as the CPU Only physical addresses leave the CPU/MMU chip

Disk controller
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Paging
Physical memory conceptually divided into fixed sized blocks called page frames. User program also divided into set of blocks of same size called pages. Allocation of memory -> finding sufficient unused frames to load user program. Address translation mechanism to map virtual pages to frames facilitated by Page Table.
pages
6064K 5660K 5256K 4852K 4448K 4044K 3640K 3236K 2832K 2428K 2024K 1620K 1216K 812K 48K 04K

6 5 1

3 0 4 7

frames
2832K 2428K 2024K 1620K 1216K 812K 48K 04K

Virtual address space

Physical memory

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Whats in a page table entry?

Protection D R V Page frame number

Dirty bit

Referenced bit

Valid bit

Each entry in the page table contains

Page frame number: page in physical memory Valid bit: set if this logical page number has a corresponding physical frame in memory If not valid, remainder of PTE is irrelevant Referenced bit: set if data on the page has been accessed Dirty (modified) bit: set if data on the page has been modified Protection information

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Address translation - Example

16 bytes divided into 2 sets, each of size 8 bytes Byte 12 : 10112 =>
Set : 1 Offset: 011

Set 1

Set 0

1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000

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Address translation Example

16 bytes divided into 4 sets, each of size 4 bytes Byte 12 :10112 =>
Set : 10 Offset: 11
Set 01 Set 11

Set 10

Set 00

1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000

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Address translation Example

Set 111

16 bytes divided into 8 sets, each of size 2 bytes Byte 12 : 10112 =>
Set : 101 Offset: 1

Set 110 Set 101 Set 100

Set 011 Set 010 Set 001 Set 000

1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000

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Page Tables -Example

Internal operation of MMU with 16 pages of 4 KB size 4 bits

12 bits

p
f

d d
12 bits

3 bits

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Mapping virtual => physical address

Split address from CPU into two pieces
Page number (p) Page offset (d)

Example: 4 KB (=4096 byte) pages 32 bit virtual addresses 2d = 4096 d = 12

Page number
Index into page table Page table contains base address of page in physical memory

32-12 = 20 bits

12 bits

Page offset
Added to base address to get actual physical memory address

Page size =

2d

bytes

32 bit virtual address

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Address translation architecture

page number Page frame number page offset 0 1 Page frame number

CPU

d 0 1 p-1 p p+1

. . .

. . .
f page table

physical memory
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. . .

f-1 f f+1 f+2

Two-level page tables

Problem: page tables can be too large
232 bytes in 4KB pages need 1 million PTEs

220 657

. . .

Solution: use multi-level page tables

Page size in first page table is large (megabytes)

401

. . .
1st level page table

125 613

1st level page table has pointers to 2nd level page tables 2nd level page table has actual physical page numbers in it

. . .

961

. . . . . . . . . . . . . . . . . . . . . . . . . . . main memory
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884 960
2nd level page tables

. . .

955

Two-level page tables

Manipal University Manipal campus KMC, MIT, Basic sciences, Admin, hostel, quarters MIT Campus Academic Blocks 1,2,3,4,5
Trauma OPD
KMC MIT

. . .

LH B1 B2

. . .

Admin

. . .

B5

. . . . . . . . . . . . . . . . . . . . . . . .
LG01

884 960

. . .

955
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Two-level paging: example

page number page offset

System characteristics p1 = 10 bits p2 = 9 bits offset = 13 bits 8 KB pages 32-bit logical address divided into 13 bit page offset, 19 bit page number Page number divided into: 10 bit page number 9 bit page offset Logical address looks like this: p1 is an index into the 1st level page table p2 is an index into the 2nd level page table pointed to by p1
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2-level address translation example

page number page offset p1 = 10 bits p2 = 9 bits offset = 13 bits frame number 0 1

Page table base

physical address

0
1 p1

19

13

. . . . . .

0 1 p2

. . .

. . .
. . .

. . .
main memory

1st level page table

2nd level page table

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Implementing page tables in hardware

Page table resides in main (physical) memory CPU uses special registers for paging Page table base register (PTBR) points to page table Page table length register (PTLR) contains length of page table: restricts maximum legal logical address Translating an address requires two memory accesses First - reads page table entry (PTE) Second - reads the data / instruction from memory Reduce number of memory accesses Cant avoid second access (need value from memory) Eliminate first access by keeping a hardware cache (a translation lookaside buffer or TLB) of recently used page table entries 34

 Search the TLB for the desired logical page number

Search entries in parallel

Translation Lookaside Buffer (TLB)

Logical page # Physical frame #

If desired logical page number is found, get frame number from TLB If desired logical page number isnt found
Get frame number from page table in memory Replace an entry in the TLB with the logical & physical page numbers from this reference

8 unused 2 3 12 29 22 7

3 1 0 12 6 11 4

Example TLB
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TLBs Translation Lookaside Buffers

A TLB to speed up paging

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Address translation
Page # Offset
TLB C

Virtual Address

yes
Page in Cache ?

i j k

400 600 900

C

No PMTBR yes <= PMTLR +

a i j k

200 400 600 900

Main Memory
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No Memory Violation

Page Map Table

Handling TLB misses

If PTE isnt found in TLB, OS needs to do the lookup in the page table Lookup can be done in hardware or software Hardware TLB replacement
CPU hardware does page table lookup Can be faster than software Less flexible than software, and more complex hardware

Software TLB replacement

OS gets TLB exception Exception handler does page table lookup & places the result into the TLB Program continues after return from exception Larger TLB (lower miss rate) can make this feasible
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Demand Paging
Bring a page into memory only when it is needed.
Less I/O needed Less memory needed Faster response More users

Page is needed reference to it

illegal reference abort not-in-memory bring to memory
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Page table entry says Invalid page !!!

Memory abort exception thrown - also called Page fault OS fetches the required page from the disk OS may have to evict some other pages loaded in the frames to make room for the pages in demand Page replacement algorithms LRU, FIFO, Optimal
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Page Fault - steps

If there is ever a reference to a page, first reference will trap to OS page fault OS looks at another table to decide: Illegal reference abort. Just not in memory. Get empty frame. Swap page into frame. Reset tables, validation bit = 1. Restart instruction
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What happens if there is no free frame?

Page replacement find some page in memory, but not really in use, swap it out.
algorithm performance want an algorithm which will result in minimum number of page faults.

Same page may be brought into memory several times.

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Page Replacement
Page replacement completes separation between logical memory and physical memory large virtual memory can be provided on a smaller
physical memory.

Use modify (dirty) bit to reduce overhead of page transfers

only modified pages are written to disk.
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Page-Replacement Algorithms
Want lowest page-fault rate. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string.

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First-In-First-Out (FIFO) Algorithm

Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5 1 1 2 1 2 3
1 2 3

4 2 3
4

4 1 3
5

4 1 2
6

5 1 2
7

5 3 2
8

5 3 4
9

1
2

1
2 3

1
2 3

5 1 3

5 1 2

5 1 2

4 1 2

4 5 2

2
3 4
5

4
1 2 3 4

4
6

4
7

3
8

3
9

3
10

Beladys Anomaly :

more frames more page faults!

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5, 2, 3
1 2 3 4 1 2 3 4 5 4

6 page faults
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Least Recently Used (LRU) Algorithm

Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5 Counter implementation
Every page entry has a counter; every time page is referenced through this entry, copy the clock into the counter. When a page needs to be changed, look at the counters to determine which are to change.
1 1 2 3 5 3 4 5

2
3 4

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Allocating memory
Search through region list to find a large enough space Suppose there are several choices: which one to use? First fit: the first suitable hole on the list Next fit: the first suitable after the previously allocated hole Best fit: the smallest hole that is larger than the desired region (wastes least space?) Worst fit: the largest available hole (leaves largest fragment) Option: maintain separate queues for different-size holes Allocate 20 blocks first fit Allocate 12 blocks next fit 1 Allocate 13 blocks best fit Allocate 15 blocks worst fit 5 18

19 14

52 25

- 102 30
- 411 19

- 135 16
- 510 3
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- 202 10

- 302 20

- 350 30 15

Shared Pages
Shared code Read-only (reentrant) code shared among processes Shared code appeared in same location in the physical address space Private code and data Each process keeps a separate copy of the code and data, (e.g., stack). Private page can appear anywhere in the physical address space. Copy on write Pages may be initially shared upon a fork They will be duplicated upon a write 49

External Fragmentation
process1
Cant fit Problem Total memory space exists to satisfy a request, but it is not contiguous. Solution Compaction: shuffle the memory contents to place all free memory together in one large block Relocatable code Expensive Paging: Allow noncontiguous logical-tophyiscal space mapping.
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Shift up

process3

process2

Internal Fragmentation
Process0 Page 0 Process0 Page 1 Process0 Page 2 Partially used 0 Process1 Full pages! Page 0 Process1 Page 1 Process1 Page 0 Page 2 Partially used Process2 Page 1 Process2 Page 2 Partially used 0

Process3 Logical space

Problem Logical space is not always fit to a multiplication of pages. (In other words, the last page has an unused portion.) Solution Minimizing page size Side effect: causes frequent page faults and TLB misses
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Protection
By using PMTLR and PMTBR

By adding access bits to the PMT entries.

Sharing
Make an entry of sharable page in every processes Page Map Table

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Paging : Advantages
1. Does not require consecutive set of memory location to load the program in main memory. 2. Does not suffer from external fragmentation. 3. Utilization of memory is quite high. 4. Supports Multiprogramming.

53

Paging : Disadvantages
1. Wastage of memory due to per-process PMT and a system wide MMT 2. Internal fragmentation 3. Extra hardware is required to speed up the memory access operation.

54

More
4. Program viewed as linear array of bytes 5. User views program as collection of variable sized logical units 6. Sharing and protection physical not logical

Solution => Segmentation

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Why use segmentation?

Virtual address space
Call stack
Constants

Different units in a single virtual address space

Each unit can grow How can they be kept apart? Example: symbol table is out of space

Allocated
Source text Symbol table

In use

Solution: segmentation
Give each unit its own address space
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Using segments
Each region of the process has its own segment Each segment can start at 0
Addresses within the segment relative to the segment start

Virtual addresses are <segment #, offset within segment>

20K 16K 12K 8K 4K 0K 16K

Symbol table

12K 8K 4K

12K

Source text

8K 4K Constants

8K 4K 0K

Call stack
Segment 3
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Segment 0

0K

Segment 1

0K

Segment 2

Paging vs. segmentation

What?
Need the programmer know about it? No How many linear address 1 spaces? More addresses than physical memory? Separate protection for different objects? Variable-sized objects handled with ease? Is sharing easy? Yes No No No

Paging

Segmentation
Yes Many Yes Yes Yes Yes

Why use it?

More address space Break programs into without buying more logical pieces that are memory handled separately.

58

Implementing segmentation
Segment 3 (10 KB) Segment 2 (4 KB) Segment 3 (10 KB) Segment 2 (4 KB) Segment 4 (7 KB) 5 KB free Segment 0 (6 KB) Segment 5 (6 KB) 4 KB free Segment 2 (4 KB) Segment 4 (7 KB) 5 KB free Segment 0 (6 KB) Segment 6 9 KB free (8 KB) Segment 5 (6 KB) Segment 2 (4 KB) Segment 4 (7 KB) Segment 0 (6 KB)

Segment 1 (12 KB)

Segment 0 (6 KB)

Segment 6 (8 KB)

=> Need to do memory compaction!

59

Protection, Sharing : Segmentation

Protection - achieved by implementing various flags in each segment table entry: Read only Read/Write Unlike a page, a segment has an entire code. Thus, sharing code is achieved by having each process code segment mapped to the same physical space.
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Segment to linear address

Selector identifies segment descriptor
Limited number of selectors available in the CPU
Selector Offset

Offset added to segments base address Result is a virtual address that will be translated by paging

Base Limit Other info

32-bit linear address

61

Better: segmentation and paging

62

Translating an address: MULTICS

63

Other benefits of VM
Shared Pages / Memory mapped files Copy On Write

64

Memory Mapped files

65

Copy-On-Write
Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. If either process modifies a shared page, only then is the page copied.

COW allows more efficient process creation as only modified pages are copied.
Free pages are allocated from a pool of zeroed-out pages.

66

Review
What is meant by memory management ? What are the responsibilities of memory manager ? What are the design constraints ? Difference between
physical memory and real memory Virtual and physical memory

Different techniques to track memory usage Different memory allocation policies Why is multiprogramming needed? What restricts the degree of multiprogramming ?
67

Review
Adv and Disadv and how to drawbacks of following techniques ?
Monoprogramming Fixed partitioning Dynamic partitioning

overcome

What is meant by virtual memory? Why is it needed? What is meant by internal and external fragmentation What is meant by compaction ?
68

Review
Paging

Basic principle Address translation Page table entry details Benefits and Drawbacks
What is meant by 2-level page table? How is it useful? What is meant by inverted page table? How is it useful?

What is meant by associative memory ?How is it useful? What are the hardware supports needed for paging? Benefits and drawbacks of big and small page sizes How is sharing and protection achieved in Paging? What is meant by PMT and MMT ? What is meant by demand paging, page fault, page replacement and Beladys anamoly?

69

Review
Segmentation
Basic principle Address translation Benefits and Drawbacks Paged segmentation, benefits , address translation How is sharing and protection achieved in Paging? Hardware support needed for segmentation

Page replacement policies

70

Review
Compare features of paging and segmentation What are the other benefits of virtual memory? What is meant by
Thrashing COW Memory mapped files
71

Numerical Problems
Memory allocation and Page replacement

72

Prob #1
Consider a page size of 100 bytes and the following memory address reference string: 120, 220,312, 423, 211, 115, 543, 653, 234, 167, 278, 190, 225, 321, 765, 666, 333, 222, 111, 249, 339, 666 How many page faults would occur for the following replacement algorithms, assuming 4 page frames? LRU replacement FIFO replacement Optimal replacement.
73

Prob #2
Consider a swapping system in which memory consists of the following hole sizes in memory order: 10K, 4K, 20K, 18K, 7K, 9K, 12K, and 15K. Which hole is taken for successive memory requests of 12K, 10K, 9K, 14K for the best fit, first fit and worst fit policies.

74

Prob #3
Given memory partitions of 100K, 500K, 200K, 300K, 150K and 600K (in order), how would each of the First-fit, Best-fit algorithms place the memory segments of processes of 156K, 120K 212K, 417K, 112K and 426K (in order)? Which algorithm makes most efficient use of memory?

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END

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