Performance Directed Synthesis For Table Look Up Programmable Gate Arrays

Amol Harkare (2011H123034G) Paritosh Peshwe(2011H123032G) Abhishek Joshi(2011H140052G) Saurabh Gupta(2011H140056G)

Programmable Gate Arrays

Programmable gate array (PGA) is an integrated circuit that can be programmed after manufacturing. Used in the design of specialized ICs that can later be produced hard-wired in large quantities.

Optimization in PGA
Area optimization :
Minimizing number of blocks

Delay optimization :
Minimizing node and wiring delay.

Delay optimization
Main considerations are number of levels in the circuit and wiring delay. We propose two phase approach :
Phase 1: Delay optimizations during logic synthesis before placement. Phase 2: Use of logic re-synthesis during a timingdriven placement technique.

Introduction

 CLU block Types of interconnects

Long lines Direct interconnect General purpose interconnect

 Interconnection programmed using passtransistors Main constraints from the synthesis viewpoint:
Maximum number of inputs to a CLB Limited wiring resources Limited number of CLB's on a chip

Definitions
Support of a function f = sup(f) = set of variables f explicitly depends on. Function f is feasible if |sup(f)| m. Slack at node is the difference between the required time and arrival time at the node. A node is critical if its slack is most negative slack in the network.

Phase I
Delays are most important factor and it is often estimated after the trade-off between the number of levels and the number of nodes and edges. Objective of this phase is to reduce the number of levels in this network. Process is called as TLU_reduce_depth.

 Steps :
Assign the level value of primary node and the level of any other node is +1 of max level of its fan-ins. It traverses from inputs and tries to collapse a critical node n. Level is reduces by collapse and re-decomposition of that network.

fig2: (a) is the original network diagram fig2: (b) is the diagram after the collapsing of the node in original network.

Reducing the level by collapsing and redecomposing is shown in figure below : fig3: (a) is the original network diagram

PHASE
The starting network for this phase is the output generated by the first phase. we use the logic synthesis n forced directed placement techniques. For logic synthesis two techniques are used
Decomposition. Partial collapse.

Delay models
Used to perform the delay computations. To compute delay we can use two methods: 1) Elmore delay model 2) penfield-rubinstein delay model Either one can be used for evaluation of delay effect.

Elmore delay model

In Elmore delay the transformations used for evaluating the effects are:
A swap of contents of two locations in the same level. Logic synthesis operations on the critical nodes.

Cost Fuction
Generally delay Increases as temperature decreases. The change in the cost function c is computed as :

Where, l is length, d is delay. (T) is a temperature dependent weight for delay

Logic Synthesis
Identifying the critical nodes we go for the logic re-synthesis. In logic synthesis we are performing two operations: 1. Decomposition. 2. Partial collapse.

Decomposition
In decomposition every block including the critical node is place according to force directed technique.

The block delay assumed to be the 2 units. As we can see the signals a and b are arriving late in the network so to correct it forcing them near the output. decomposition as i = cde and g = i (a+b).

Partial collapse
In partial collapse by transformations we are reducing the delays.

Node delay is 2 and interconnects delay is 1 and 2. n is collapse.

Conclusion
Mis-pga performs better than chrotle-d for the lower level synthesis. In this technique re-synthesis is the main process which results in delay improvement. However, in many cases there is very less scope for delay improvement.

References
K. J. Singh, A. R. Wang. R. K. Brayton, and A. Sangiovanni-VincenteIli. Timing Optimization of Combinational Logic, Proc. ICCAD. Nov. 1988. pp. 282-285. J. Kubinstein. P. Penfield. and M. A. Horowitz. Signal Delay in RC Tree Net-works, IEEE TransacfionsonCAD, July 1983, pp. 119-127. R. Murgai, N.Shenoy,R. K. BraytonandA. Sangiovanni-Vincentel~,Improved Logic Synthesis Algorithms for Table Look Up Architectures, Prm. ICCAD. Nov. 1991.

Thank You.