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HARINI
AIM
To have an in depth knowledge of the architecture and programming of 8-bit and 16-bit Microprocessors, Microcontrollers and to study how to interface various peripheral devices with them.
OBJECTIVE
To study the architecture and Instruction set of 8085 and 8086 To develop assembly language programs in 8085 and 8086. To design and understand multiprocessor configurations To study different peripheral devices and their interfacing to 8085/8086. To study the architecture and programming of 8051 microcontroller.
UNIT I THE 8085 AND 8086 MICROPROCESSORS 8085 Microprocessor architecture-Addressing modes- Instruction set-Programming the 8085 UNIT II 8086 SOFTWARE ASPECTS Intel 8086 microprocessor - Architecture - Signals- Instruction Set-Addressing ModesAssembler Directives- Assembly Language Programming-Procedures-MacrosInterrupts And Interrupt Service Routines-BIOS function calls. UNIT III MULTIPROCESSOR CONFIGURATIONS Coprocessor Configuration Closely Coupled Configuration Loosely Coupled Configuration 8087 Numeric Data Processor Data Types Architecture 8089 I/O Processor Architecture Communication between CPU and IOP. UNIT IV I/O INTERFACING Memory interfacing and I/O interfacing with 8085 parallel communication interface serial communication interface timer-keyboard/display controller interrupt controller DMA controller (8237) applications stepper motor temperature control. UNIT V MICROCONTROLLERS Architecture of 8051 Microcontroller signals I/O ports memory counters and timers serial data I/O interruptsInterfacing -keyboard, LCD,ADC & DAC
UNIT I
The first microprocessor was introduced in 1970 by Intel (named 4004). It ran at the speed of 108KHz. Four years later, Intel created the 8080 running at just over 2 Mhz. This microprocessor was used on the world's firs personal computer, named Altair. Also at this time, IBM started researching for their microprocessor, called POWER (Performance Optimization With Enhanced RISC).
Machine Control
BASED ON LENGTH One-word or 1-byte instructions Two-word or 2-byte instructions
Between Registers Between Memory location and a Registers Direct write to a Register/Memory Between I/O device and Accumulator
Logic operations
Branching operations (JMP, CALL, RET)
PIN DIAGRAM
UNIT- II
Intel 8086 microprocessor Architecture Signals Instruction set Addressing modes Assembler directives Assembly language programming Procedures
Macros
Interrupts and interrupt service routines. BIOS Function Calls
8086 FEATURES
16-bit Arithmetic Logic Unit 16-bit data bus (8088 has 8-bit data bus)
16-bit Registers
Ge ne ral Purpose
AH AL
Inde x BP SP
AX
BH
BL
BX
SI
CH CL
CX
DI
DH
DL
DX
8086 ARCHITECTURE
The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU fetches instructions, reads and writes data, and computes the 20-bit address.
The EU decodes and executes the instructions using the 16-bit ALU. The BIU contains the following registers:
IP - the Instruction Pointer CS - the Code Segment Register DS - the Data Segment Register SS - the Stack Segment Register ES - the Extra Segment Register
The BIU fetches instructions using the CS and IP, written CS:IP, to contract the 20-bit address. Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode.
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmers Model
ES CS SS DS IP AX BX CX DX AH BH CH DH SP BP SI DI FLAGS AL BL CL DL
Extra Segment Code Segment Stack Segment Data Segment Instruction Pointer Accumulator Base Register Count Register Data Register Stack Pointer Base Pointer Source Index Register Destination Index Register
EU registers
AX, BX, CX and DX are two bytes wide and each byte can be accessed separately
These registers are used as memory pointers.
Segment registers are used as base address for a segment in the 1 M byte of memory
Registers
Registers are in the CPU and are referred to by specific names Data registers
Hold data for an operation to be performed There are 4 data registers (AX, BX, CX, DX)
Address registers
Hold the address of an instruction or data element Segment registers (CS, DS, ES, SS) Pointer registers (SP, BP, IP) Index registers (SI, DI)
Status register
Keeps the current status of the processor On an IBM PC the status register is called the FLAGS register
Instructions execute faster if the data is in a register AX, BX, CX, DX are the data registers Low and High bytes of the data registers can be accessed separately
AH, BH, CH, DH are the high bytes AL, BL, CL, and DL are the low bytes
Data Registers are general purpose registers but they also perform special functions AX
Accumulator Register Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code Must be used in multiplication and division operations Must also be used in I/O operations
BX
Base Register Also serves as an address register Used in array operations Used in Table Lookup operations (XLAT)
CX
Count register Used as a loop counter Used in shift and rotate operations
DX
Data register Used in multiplication and division Also used in I/O operations
Contain the offset addresses of memory locations Can also be used in arithmetic and other operations SP: Stack pointer
Used with SS to access the stack segment
The SI and the DI registers may also be used to access data stored in arrays
Are Address registers Store the memory addresses of instructions and data Memory Organization
Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1 meg of addressable memory Addresses are expressed as 5 hex digits from 00000 - FFFFF Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers! Solution: Memory Segment
Block of 64K (65,536) consecutive memory bytes A segment number is a 16 bit number Segment numbers range from 0000 to FFFF Within a segment, a particular memory location is specified with an offset
Segmented Memory
Segmented memory addressing: absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
F0000 E0000 D0000 C0000 B0000 A0000 90000 80000 70000 60000 50000 40000 30000 20000 10000 00000 seg ofs 8000:0000
0250
8000:FFFF
one segment
8000:0250
Intel
The BIU has a dedicated adder for determining physical memory addresses
Offset Value (16 bits)
0000
Adder
Intel
If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data?
2 Offset:
Segment:
Address:
SEGMENT:OFFSET ADDRESS
Logical Address is specified as segment:offset Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address Thus the physical address of the logical address A4FB:4872 is
A4FB0 + 4872 A9822
EXAMPLE
CS:
0400H IP 0056H
4000H 4056H
0H
Memory
0FFFFFH
The offset is the distance in bytes from the start of the segment. The offset is given by the IP for the Code Segment. Instructions are always fetched with using the CS register.
The physical address is also called the absolute address.
0H
DS:
05C0
EA 0050
05C0
0050
05C50H
0FFFFFH
Physical Address
Data is usually fetched with respect to the DS register. The effective address (EA) is the offset. The EA depends on the addressing mode.
0H
SS:
0A00
0A000H SP 0100
0A100H
SS:SP
Memory
0A00 0
+ 0100 0A100H
Physical Address
0FFFFFH
The offset is given by the SP register. The stack is always referenced with respect to the stack segment register. The stack grows toward decreasing memory locations. The SP points to the last or top item on the stack. PUSH - pre-decrement the SP POP - post-increment the SP
Flags
Flag Register
Conditional flags: They are set according to some results of arithmetic operation. You do not need to alter the value yourself. Control flags: Used to control some operations of the MPU. These flags are to be set by you in order to achieve some specific purposes.
Flag Bit no. 15 14 13 12 O 11 D 1 0 I 9 T 8 S 7 Z 6 5 A 4 3 P 2 1 C 0
CF (carry) Contains carry from leftmost bit following arithmetic, also contains last bit from a shift or rotate operation.
Flag Register
ignored.
TF (trap) Permits operation of the processor in single step mode.
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative) ZF (zero) Indicates when the result of arithmetic or a comparison is zero. (1=yes) AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic.
PF (parity) Indicates the number of 1 bits that result from an operation.
Macros
avoid repetitious SAS code create generalizable and flexible SAS code pass information from one part of a SAS job to another conditionally execute data steps and PROCs dynamically create code at execution time
Example
Simple macro variable %let dsn=LAB; title "DATA SET &dsn"; proc contents data=&dsn; run; proc print data=&dsn(obs=10); run;
Procedures
Initial call to run an external program
Instruction Set
Mov destination, source add, inc, dec and sub instructions Input/Output String Instructions Machine Control Flag Manipulation.
Addressing Modes
Immediate addressing.
Register addressing.
Direct addressing. Indirect addressing Implied addressing. Indexed addressing
Relative addressing
MAXIMUM MODE
Maximum mode Maximum mode is designed to be used with a coprocessor exists in the system.
All the control signals (except RD) are not generated by the microprocessor.
But we still need those control signals. Solution: 8288.
S2
S1 S0
operation
signal
0 0
0 0
0 0
1 1
0 1
0 1
INTA IORC
none
IOWC, AIOWC
1
1 1 1
0
0 1 1
0
1 0 1
Instruction Fetch
Read Memory Write Memory Passive MRDC MWTC, AMWC none
MRDC
UNIT III
Coprocessor Configuration Closely Coupled Configuration Loosely Coupled Configuration 8087 Numeric Data Processor-architecture Data types 8089 I/O Processor-Architecture Communication between CPU and IOP
Architecture of 8087
Two Units Control Unit Execution Unit
Control Unit
Control unit: To synchronize the operation of the coprocessor and the processor. This unit has a Control word and Status word and Data Buffer If instruction is an ESCape (coprocessor) instruction, the coprocessor executes it, if not the microprocessor executes. Status register reflects the over all operation of the coprocessor.
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit B-Busy bit indicates that coprocessor is busy executing a task. Busy can be tested by examining the status or by using the FWAIT instruction. C3-C0 Condition code bits indicates conditions about the coprocessor. TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack. ES-Error summary bit is set if any unmasked error bit (PE, UE, OE, ZE, DE, or IE) is set. In the 8087 the error summary is also caused a coprocessor interrupt. PE- Precision error indicates that the result or operand executes selected precision. UE-Under flow error indicates the result is too large to be represent with the current precision selected by the control word. OE-Over flow error indicates a result that is too large to be represented. If this error is masked, the coprocessor generates infinity for an overflow error. ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number. DE-Denormalized error indicates at least one of the operand is denormalized. IE-Invalid error indicates a stack overflow or underflow, indeterminate from (0/0,0,-0, etc) or the use of a NAN as an operand. This flag indicates error such as those produced by taking the square root of a negative number.
CONTROL REGISTER
Control register selects precision, rounding control, infinity control. It also masks an unmasks the exception bits that correspond to the rightmost Six bits of status register. Instruction FLDCW is used to load the value into the control register.
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC Infinity control selects either affine or projective infinity. Affine allows positive and negative infinity, while projective assumes infinity is unsigned. INFINITY CONTROL
0 = Projective 1 = Affine
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL 00=Single precision (short) 01=Reserved 10=Double precision (long) 11=Extended precision (temporary) Exception Masks It Determines whether the error indicated by the exception affects the error bit in the status register. If a logic1 is placed in one of the exception control bits, corresponding status register bit is masked off.
Data Types
Internally, all data operands are converted to the 80-bit temporary real format. We have 3 types. Integer data type Packed BCD data type Real data type Example Converting a decimal number into a Floating-point number. 1) Converting the decimal number into binary form. 2) Normalize the binary number 3) Calculate the biased exponent. 4) Store the number in the floating-point format. Example Step Result 1) 100.25 2) 1100100.01 = 1.10010001 * 26 3) 110+01111111=10000101 4 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110,plus a bias of 01111111(7FH) single precision no use 7F and double precision no use 3FFFH. IN step 4 the information found in prior step is combined to form the floating point no.
UNIT V
Architecture of 8051 Signals Operational features Memory and I/O addressing Interrupts Instruction set Applications.
Microcontroller :
A smaller computer On-chip RAM, ROM, I/O ports... ExampleMotorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X
CPU
RAM ROM
A single chip
I/O Port
Serial Timer COM Port Microcontroller
Microcontroller CPU, RAM, ROM, I/O and timer are all on a single chip fix amount of on-chip ROM, RAM, I/O ports for applications in which cost, power and space are critical single-purpose
Block Diagram
External interrupts Interrupt Control On-chip ROM for program code
Timer/Counter
On-chip RAM
Timer 1 Timer 0
Counter Inputs
CPU
Serial Port
OSC
Bus Control
4 I/O Ports
P0 P1 P2 P3
TxD RxD
Address/Data
8051 (8031)
19
10 K
P0.0 DS5000 P0.1 P0.2 8751 P0.3 P0.4 8951 P0.5 P0.6 P0.7
Port 0
Registers
A B R0 R1 R2 R3 R4 R5 R6 Some 8051 16-bit Register PC PC DPTR DPH DPL
Bit-Addressable RAM
20H 1FH 18H 17H 10H 0FH 08H 07H 00H
Timer: :
Timer :
Interrupt :
Hexadecimal Basis
Hexadecimal Digits: 1 2 3 4 5 6 7 8 9 A B C D E F
MOV Rn, A ;n=0,..,7 ADD A, Rn MOV DPL, R6 MOV DPTR, A MOV Rm, Rn
MOV A,#65H
MOV R6,#65H
MOV DPTR,#2343H MOV P1,#65H
; bit=1 ; bit=0
; CY=1 ;bit 0 from port 0 =1 ;bit 7 from port 3 =1 ;bit 2 from ACCUMULATOR =1 ;set high D5 of RAM loc. 20h
CLR instruction is as same as SETB i.e.: CLR C ;CY=0 But following instruction is only for CLR: CLR A ;A=0
DEC INC
INC DEC DEC
byte byte
R7 A 40H
;byte=byte-1 ;byte=byte+1
; [40]=[40]-1
Jump if A=0
Jump if A/=0 Decrement and jump if A/=0
CJNE A,byte
CJNE reg,#data JC JNC JB JNB JBC
Jump if A/=byte
Jump if byte/=#data Jump if CY=1 Jump if CY=0 Jump if bit=1 Jump if bit=0 Jump if bit=1 and clear bit
Call instruction
UNIT IV
Memory Interfacing and I/O interfacing Parallel communication interface Serial communication interface Timer Keyboard /display controller Interrupt controller DMA controller
Memory-mapped I/O
Reading and writing are similar to memory read/write Uses same memory read and write signals Most processors use this I/O mapping
Isolated I/O
Separate I/O address space Separate I/O read and write signals are needed Pentium supports isolated I/O
64 KB address space Can be any combination of 8-, 16- and 32-bit I/O ports Also supports memory-mapped I/O
accumulator, port8
Useful to access first 256 ports
in
accumulator,DX
DX gives the port address
ins: port address in DX, memory address in ES:(E)DI outs: port address in DX, memory address in ES:(E)SI We can use rep prefix for block transfer of data
Scan code is like a sequence number of the key Keys scan code depends on its position on the keyboard No relation to the ASCII value of the key
Keyboard scan code and status can be read from port 60H
An end-notification phase
Programmed I/O Interrupt
Done by busy-waiting
This process is called polling
Example
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 19.1 uses this process to read input from the keyboard
DMA
Frees the processor of the data transfer responsibility
DMA controller
Acts as slave to processor
Processor gives details to the DMA controller I/O device number Main memory buffer address Number of bytes to transfer Direction of transfer (memory I/O device, or vice versa)
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read, loops back to repeat the process
Mode register
Each channel can be programmed to
Request register
For software-initiated DMA
Mask register
Used to disable a specific channel
What is a Timer?
A device that uses highspeed clock input to provide a series of time or count-related Counter Register events System Clock 0x1206
Reload on Zero
000000
Countdown Register I/O Control
Low Byte
GO Register
offset 0x08, immediately moves Counter Reg value into Current Counter
Current Counter
(not directly readable by software)
Latch Register
offset 0x0C, write a ``1'' to immediately write Current Counter value to readable Latch Reg
Latched Counter
at offsets 0x04, 0x00 (read only)
To program the timer to reach zero 100 times per second Example: For a 2 MHz-based timer, 2MHz / 100 = 20,000
0x10200050
Polled I/O requires the CPU to ask a device (e.g. toggle switches) if the device requires servicing For example, if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be serviced Interrupt I/O allows the device to interrupt the processor, announcing that the device requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time therefore, software has no idea when an interrupt will occur This makes it more difficult to write code Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs. FIQ)
To disable interrupts, set the corresponding F or I bit to 1 On interrupt, processor switches to FIQ32_mode registers or IRQ32_mode registers
On any interrupt (or) Switch register banks Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits
SWI Trap
INTERFACING
Static RAM interfacing. Procedure Configuration. Dynamic RAM interfacing.
PIO 8255
a) b) i) ii) iii) Programmable input output Port. Architecture Signals Modes Of Operation BSR Mode I/O Modes Mode 0(Basic I/O Mode) Mode 1 (Strobed I/O Mode) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller. Architecture and Signal Descriptions Interrupt Sequence . Command word a) Initialization Command word (ICWs). b) Operation Command words. Modes of operation: 1.Nested mode. 2.Fully Nested Mode. 3.Poll mode Automatic EOI Mode.
8251 USART
Methods of Data communication a) Simplex b) Duplex c) Half Duplex Architecture Control Word a) Mode Instruction control word b) Command instruction control word
TEXT BOOKS
Ramesh S.Gaonkar, Microprocessor - Architecture, Programming and Applications with the 8085, Penram International publishing private limited, fifth edition. (UNIT-1: Chapters 3,5,6 and programming examples from chapters 7-10) A.K. Ray & K.M.Bhurchandi, Advanced Microprocessors and peripherals- Architectures, Programming and Interfacing, TMH, 2002 reprint. (UNITS 2 to 5: Chapters 1-6, 7.1-7.3, 8, 16)
REFERENCES
Douglas V.Hall, Microprocessors and Interfacing: Programming and Hardware, TMH, Third edition Yu-cheng Liu, Glenn A.Gibson, Microcomputer systems: The 8086 / 8088 Family architecture, Programming and Design, PHI 2003 Mohamed Ali Mazidi, Janice Gillispie Mazidi, The 8051 microcontroller and