().

C6000

C6000 for ICT

TMS320C6000 DSP Family

VLIW Architecture Very Long Instruction Word Parallel processing with multiple function units TMS320C6000 Family Fixed-Point C6x DSP Floating-Point C6x DSP

C6000 for ICT

Fixed-Point C6x DSP

TMS320C62x
TMS320C6201 TMS320C6202 TMS320C6203 TMS320C6211

TMS320C64x: Designed for 3G wireless and broadband infrastructure, as well as imaging/video applications
TMS320C6411 TMS320C6414 TMS320C6415 TMS320C6416 TMS320DM640 TMS320DM641 TMS320DM642

C6000 for ICT

Floating-Point C6x DSP

TMS320C67x TMS320C6701 TMS320C6711 TMS320C6712 TMS320C6713

C6000 for ICT

Software-Compatible C6x DSP Platform

C62x Fixed-Point DSP Generation Clock Rate (MHz) MIPS/MFLOPS 150-300 1200-2400 MIPS C64x Fixed-Point DSP Generation 600-1100 4800-8800 MIPS C67x Floating-Point DSP Generation 150-300 600-1000 MFLOPS

16-bit MMACS 8-bit MMACS Broadband Communications Imaging

300-600 300-600 General

3400-4400 4800-8800 Special-purpose Instructions Special-purpose Instructions

300-333 300-333 General

General

General

C6000 for ICT

The Block Diagram of C6x

Core CPU
Eight Functional Units 32 32-bit Registers Data-Path Control Unit

On Chip Peripherals On Chip Memory

Data RAM Program RAM

Internal Buses and EMIF

C6000 for ICT

C6000 System Block Diagram

Program RAM 256
Internal Buses DMA/EDMA Serial Port

Address

Data RAM

XB

EMIF

Data

.D1

.D2

HPI Boot Load Timer/Counter Pwr Down

Regs A

Regs B

External Memory -Sync --Async

.M1 .M2 ..L1 .S1 .L2 .S2

Control Regs

C6000 for ICT

TMS320C6713 Key Features

C6713 Launched at 200/300MHz; 1200/1800 MFLOPS Executes up to 8 instructions in single cycle 72 K Cache RAM on-chip (split 4K L1 program / 4K L1 data / 64K L2 unified) 32 32-bit registers file All instructions may be conditional Efficient Compilation of C code Data is byte-addressable. (it can be 8-bit, 16-bit or 32-bit)

C6000 for ICT

TMS320C6713 DSP Block Diagram

EMIF L1 Program Memory 4K Bytes L2 Cache Memory 64K Bytes

Host Port
McBSP McBSP Timer Timer McASP*2 EDMA

C67x/C62x CPU

L1 Data Memory 4K Bytes

C6000 for ICT

C67xx Device Summary

Device 6701 6711 MHz 150/167 150/200 MFLOPS 1000 900/1200 KBytes 128 72 Pins 352 256 mm 35 27 W 1.8 1.3 $ 110-170 20-50 Periphs D2H E2H

6713

200/300

1200/1800

72

272

27

1.4

20-30

E2H

Peripherals Legend: D, E 2, 3 H,X,P

Pin-for-Pin Compatibility: 6201 & 6701 6211 & 6711 6202 & 6203 & 6204 DM640&DM641&DM642

DMA (4), EDMA (16) # of McBSP Serial Ports (6713 2*McASP) HPI (Host Por), XBUS, PCI

C6000 for ICT

10

C6x Core CPU

Program fetch unit Instruction dispatch unit Instruction decode unit Two data paths, each with four functional units Thirty-two 32-bit registers Control registers Control unit Test, Emulation and Interrupt Logic

C6000 for ICT

11

Core CPU Block Diagram

C6000 for ICT

12

C67x General Register Files

Can be used for data or data-address pointers. A1,A2, B0,B1,and B2 can be used for condition. A4~7 and B4~7 can be used for circular addressing. Support 32- and 40-bit fixed-point data. The C67x also uses these register pairs to hold 64-bit double-precision floating-point values.

C6000 for ICT

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Functional Units and Register Files

A0 A1 A2 A3 B0 B1 B2 B3

.S1 .M1 .L1 .D1

.S2 .M2 .L2 .D2

A15
Register File A

B15

Data Memory

Register File B

C6000 for ICT

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C67x Functional Units

C6000 for ICT

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Advantages of Functional Unit

Eight functional units which you can use in parallel to execute up to 8 instructions in a given cycle. If the cycle time for one instruction is 5ns (200MHz clock), this results in 1600 MIPs of performance.

C6000 for ICT

16

C67x Data Paths

Two general-purpose register files (A and B)
16 32-bit registers (A0~A15) for file A 16 32-bit registers (B0~B15) for file B.

Eight functional units

.L1, .S1, .M1 and .D1 for A .L2, .S2, .M2 and .D2 for B

Two load-from-memory paths (LD1 and LD2) Two store-to-memory paths (ST1 and ST2) Two register file cross paths (1X and 2X) Two data address paths (DA1 and DA2)

C6000 for ICT

17

Control Registers
Basic Control Registers Address Mode Register (AMR) Control Status Register (CSR) Interrupt Registers Program Counter E1 Register Floating Point Extension Register

C6000 for ICT

18

C6x Control Register

C6000 for ICT

19

C67x Control Extension Registers

C6000 for ICT

20

C6x11/C6713 Memory Map

Byte Address
0000_0000 64K8 Internal

4K Program Cache
0180_0000 On-chip Peripherals

8000_0000 9000_0000 A000_0000 B000_0000 FFFF_FFFF

0 1 2 3

128M8 External 128M8 External 128M8 External 128M8 External

CPU

64K Unified RAM (Level 2 Cache)

4K Data Cache

= reserved