RF Modeling of Sub-100 nm CMOS

S.Yoshizaki1, M.Nakagawa1, W.Y.Chong1, Y.Nara2, M.Yasuhira2*, F.Ohtsuka2, T.Arikado2**, K.Nakamura2, K.Kakushima1, K.Tsutsui1 H.Aoki1, H.Iwai1
Tokyo Institute of Technology 2 Semiconductor Leading Edge Technologies, Inc. (Selete), Japan * Current affiliation : Matsushita Electric Industrial Co., Ltd., Japan ** Current affiliation : Tokyo Electron Ltd., Japan
1

Background ~RF Technology~

Spread of the cellular phone and the wireless LAN.

The age of Digital information appliances

Fig.1 4-th Generation mobile
Center Research Laboratory, Hitachi Ltd.

RF technologies serve the rapidly growing wireless communication markets.

100%

Accurate RF Modeling become important to more than before.

But In RF, some parasitic elements effect more severe.

80% 60% 40% 20% 0% 2004 2005 2006 2007 2008 2009

Fig.2 Technology-development cost reduction (due to TCAD) ITRS2004update, 2004

Feature in RFCMOS
Merit
Low cost compared with compound semiconductors

Demerit
Low operation voltage with scaling
SN ratio degradation

Consolidation with logic circuits

Scaling and Circuit technologies improve fT and fmax

Fig.3 Application Spectrum

ITRS2004, 2004

The concern about High-k MOSFET in RF

Degradation of dielectric constant with dielectric relaxation. RF characteristic deterioration with degrading mobility.

Increase interface state density Increase Low-frequency noise and thus Phase noise.

Motivation
RF Modeling of Sub-100 nm High-k MOSFET

There

are little reports about RF performance evaluation and modeling with High-k MOSFETs. Comparison HfSiON with SiON.

Device

EOT = 1.5nm (HfSiON & SiON) Gate length HfSiON (Lg= 64nm), SiON (Lg= 51nm) The number of finger = 12W=5m

silicide
HfSiON

SiN

Si

G
Fig.4 HfSiON MOSFET structure

S
silicide
SiON SiN

S
M1 VIA1 STI S
63.9nm

Si Fig.5 SiON MOSFET structure

D
61.7nm

S
62.3nm

D
65.5nm

S
65.3nm

Increase gate width with increasing number of fingers, the gate resistance become small.

RG

W 1 Rsh tot2 3 LN f

Nf : The number of finger

Fig.6 Section of HfSiON MOSFET

DC Measurement and Simulation HfSiON

6.00E-04

Vgs=0, 0.6, 0.9, 1.2, 1.5V

5.00E-04 4.00E-04

Measured Simulated

Id/W[A]

3.00E-04 2.00E-04 1.00E-04

7.00E-04

0.00E+00 0 0.5 Vd[V] 1 1.5

Id/W[A]

6.00E-04 5.00E-04 4.00E-04 3.00E-04 2.00E-04 1.00E-04 0.00E+00 0 0.5 Vd[V] 1 1.5

Fig.7 Measured and simulated Ids-Vds HfSiON

Fig.8 Measured Ids-Vds SiON

De-embedding
To de-embed parasitic elements including wires and pads is important that could obtain the real device parameters.
Cgd Rgdp

OPEN
Drain Gate Drain
Rd Cd

Gate
Lg Cg Rs Rgp Ls Rg

Ld

BSIM4
Rdp

DUT

SHORT
Gate

Drain

Measured and Simulated fT, fmax HfSiON

50 40 30 20 10 0 0.1 1 10 Frequency[GHz] 100 1000
Measured GAmax Simulated GAmax Measured H21 Simulated H21

H21, GAmax[dB]

Vg=1.2V, Vd=1.5V

fT,HfSiON = 189.9[GHz] fmax,HfSiON = 59.9[GHz]

LD CGD

RD

Fig.9 H21 and GAmax vs. Frequency HfSiON

Rg

gm fT 2CGS

BSIM4 CGS

f max

ft 2 ( g ds ( RG RS ) 2fT RG CGD )

Fig.10 Equivalent circuit model

Measured S-parameter and Predicted fT, fmax SiON

60 50
Measured GAmax Extrapolated GAmax Measured H21 Extrapolated H21

Vg=1.2V, Vd=1.5V

H21, GAmax[dB]

40 30 20 10 0 0.1 1 10 Frequency[GHz]

fT,SiON = 236[GHz] fmax,SiON = 74[GHz]

100 1000

Fig.11 H21 and GAmax vs. Frequency SiON

RF Characterization
~ fT & gm Comparison HfSiON with SiON~
250 fTSiON fTHfSiON gmSiON gmHfSiON 100 90 80 70

200

fT[GHz]

50 100

Cross SiON and HfSiON characteristics

gm peak

40 30 20 10

50

0 0.01

0 0.1 1 Id[A] 10 100

Fig.12 fT and gm vs. Id

gm[mS]

150

60

Position of this device

300 250
fmax[GHz]

300 250 200

nmos

t f [G H z]

200 150 100

nmos

150 100 50 0

pmos

50 0 0.01

pmos

0.1

0.01

0.1

Gate Length [um] [m ] SiON HfSiON

[m ] Gate Length [um]

Fig.13 fT and fmax

IEDM, VLSI 19952004

Summary
We measured and simulated High-k MOSFET RF characteristics.

Measured from 500MHz to 40GHz, there is no dielectric relaxation.

Simulated fT and fmax in HfSiON, we obtained good fT (189.9GHz) relatively.

SiON is expected much more high performance than HfSiON. I guess this is because of mobility degradation.

Acknowledgement
This work was partially supported by Special Coordination Funds for Promoting Science and Technology by Ministry of Education, Culture, Sports, Science and Technology, Japan.

Appendix A ~Flicker noise~

nmos
1.00E-14 1.00E-15 1.00E-16 1.00E-17 1.00E-18 1.00E-19 0.01 0.1 1 10 Frequency[kHz] 100
SiON HfSiON

Sid[A^2/Hz]

Id=1mA / Vd=0.1V

Fig.14 Flicker noise

Appendix B ~RF CMOS Evaluation Equipment~

8 inch wafer, 40 GHz