ARM9 EP9315 UART

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EP9315 Features
UARTs

Three 16550 - compatible UARTs are supplied UART1 with HDLC (High-Level Data Link Control ) & modem control signals

Supports modem bit rates up to 115.2 kbps Supports HDLC and includes a 16 byte FIFO for receive and a 16 byte FIFO for transmit. Interrupts are generated on Rx, Tx and Modem status change. Contains an IrDA encoder operating at either the slow (up to 115 kbps), medium (0.576 or 1.152 Mbps), or fast (4 Mbps) IR data rates. It also has a 16 byte FIFO for receive and a 16 byte FIFO for transmit.

UART2

UART3 with HDLC encoder

HDLC interface identical to that of UART1

The ARM Architecture

ED500

TM

UART1

Block to support 9 pin modem interface

Block to support synchronous and asynchronous HDLC protocol for full duplex transmit and receive

Transmit & Receive data transfers through UART1 can be managed by the DMA, interrupt driven or CPU polled operations

The ARM Architecture

ED500

TM

UART1

Programmable Baud Rate Generator

Common tx & rx internal clock from internal ref input UARTCLK Free running counter Generate internal x 16 clocks & Baud16 signal Baud16 stream of pulses

Provides Timing for Tx & RX control Pulse width width of one UART Clock period Frequency 16 times the baud rate

Transmit FIFO

8-bit wide, 16 entry deep, first in first out Disabled to 1-byte holding register

The ARM Architecture

ED500

TM

Receive FIFO

11-bit wide, 16 entry deep, first in first out

Receive data and error bits are stored

Disabled to 1-byte holding register

Transmit Logic

Performs parallel to serial conversion on FIFO data

Serial bit stream start bit, data, parity, stop bit

Receive Logic

Performs serial to parallel conversion on received data

Parity, frame error checking and line break detection are performed. Data with parity, frame and break error is written to FIFO
ED500
TM

The ARM Architecture

UART Operation

Control data is written to UART line control register UARTLCR (23 bits wide internally) & externally accessed through 8-bit wide register locations UARTLCR_H, UARTLCR_M & UARTLCR_L Defines baud rate divisor, transmission parameters, word length, no of stop bits, parity etc.

The ARM Architecture

ED500

TM

UART Operation

Baud rate divisor is 16-bit number

Used by baud rate generator to determine the period

Baud rate generator has 16-bit down counter (clocked by the UART reference clock) When baud rate divisor is decremented to zero

Down counter is reloaded with baud rate divisor Baud 16 signal is generated (divided by 16 to generate the transmit clock)

The ARM Architecture

ED500

TM

UART Operation

Transmission

Data is written to transmit FIFO Data frame starts transmitting according to UARTLCR configuration BUSY signal is asserted HIGH until the FIFO is empty and last character is transmitted, becomes low after last character stop bit is transmitted

The ARM Architecture

ED500

TM

UART Operation
Reception

When a low is detected, receive counter with Baud16 clock is started Data is sampled on the 8th cycle of that counter Valid start bit if UARTRXD bit is low on 8th cycle of baud16 Successive data bits sampled on the every 16th cycle A valid stop bit is confirmed if UARTRXD is HIGH

When a full data word is received it is stored in receive FIFO

The ARM Architecture

ED500

TM

UART Operation
Receive FIFO (16 x 11 bits)

Data Bits 0:7 Error bits 8 - Framing error 9 - Parity error 10 - Break error Overrun error Disabling FIFOs 1- byte holding register Loop back testing setting LBE bit UARTxCtrl reg
ED500
TM

The ARM Architecture

10

10

UART PROGRAMMING TIPS

Configure PwrCnt System Control Register for UART clock

Bit 29 UART BAUD is set as 0

Clock = 14.7456 MHz /2 = 7.3728 MHz

Configure PwrCnt as 0 BAUDDIV = (Fuartclk /(16 * Baud rate))-1 For baud rate 9600, BAUDDIV=47

Configure UARTLCR_L with baud rate divisor bits- 0 to 7 lsb

Configure UARTLCR_M with baud rate divisor bits- 8 to 15

0 on reset. 0 here for 9600

Word length- no of bits per frame (Bits 6 &5)

Configure UARTLCR_H with

11 8 bits 10 7 bits 01 6 bits 00 5 bits 1 - Tx & Rx FIFO buffers are enabled 0 FIFO are disabled, ie FIFOs become 1-byte-deep holding registers

FIFO enable (Bit 4)

The ARM Architecture

ED500

TM

11

11

UART PROGRAMMING TIPS

Configure UARTLCR_H with

Two STOP bits select (Bit 3)

1 Two STOP bits are transmitted at the end of the frame 0 One STOP bit is transmitted at the end of the frame 1 - Even parity generation and checking is performed during transmission and reception which checks for an even number of 1s in data and parity bits 0 - Odd parity checking is performed which checks for add number of 1s 1 - Parity checking and generation is enabled 0 - Parity checking and generation is disabled and no parity bit is added to the data frame 1- A low level is continuously output on the UARTTXD output, after completing transmission of current character 0- for normal use

Even Parity Select (Bit 2)

Parity Enable (Bit1)

Send Brake (Bit 0)

The ARM Architecture

ED500

TM

12

12

UART1 cntrl

UART Enable (Bit0) Check if Transmit FIFO empty (Bit 7) polling method

UART1Flag

The ARM Architecture

ED500

TM

13

13

Program
#include<stdio.h> #define #define #define #define #define #define #define PWRCNT UART_DATA UART_CONTROL_HIGH UART_CONTROL_MID UART_CONTROL_LOW UART_CONTROL UART_FLAG ((volatile unsigned *)(0x80930004)) ((volatile unsigned *)(0x808C0000)) ((volatile unsigned *)(0x808C0008)) ((volatile unsigned *)(0x808C000C)) ((volatile unsigned *)(0x808C0010)) ((volatile unsigned *)(0x808C0014)) ((volatile unsigned *)(0x808C0018)) //DATA TO BE LOADED //LENGTH,FIFO..ETC. //BAUD RATE DIVISOR(MSB) //BAUD RATE DIVISOR(LSB) //INTERRUPT, "UART ENABLE"...ETC. //FLAGS

unsigned char s[]=EP9315 UART";

int main(void)
{ unsigned int i; *PWRCNT=0x00; *UART_CONTROL_LOW=0x002F; *UART_CONTROL_MID=0x0000; *UART_CONTROL_HIGH=0x0060; // 8 bit frame *UART_CONTROL=0x0001; // UART ENABLE // BAUD RATE 9600

The ARM Architecture

ED500

TM

14

14

for(i=0;i<11;i++) {

*UART_DATA=s[i];

while((*UART_FLAG & 0x08)!=0x00); // TXE not HIGH

The ARM Architecture

ED500

TM

15

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