LECTURE ON MICROCONTROLLER-8051 AND APPLICATIONS

BY G N V RATNA KISHOR M.Sc.,M.Tech. ASST. PROFESSOR

Contents:
Introduction
Block Diagram of 8051 and its architecture Registers Memory organization in 8051 Addressing modes

Instruction set
Timers Interrupts

Microprocessor

Micro controller
CPU with integrated memory and peripherals

INTELS MCS-51 Microcontrollers

Device Internal memory Program Data Timer/ Interrupts counters

8031
8032 8051 8052 8751

None
None 4k*8 ROM 8k*8 ROM

128*8 RAM 2*16 bit 5

128*8 RAM 3*16 bit 6 128*8 RAM 2*16 bit 5 256*8 RAM 3*16 bit 6

4K*8 EPROM 128*8 RAM 2*16 bit 5

Block Diagram of 8051

External interrupts ROM Interrupt Control 4 KB RAM 128Bytes
Timer/Counter

Timer 1 Timer 0

Counter Inputs

CPU
Serial Port

OSC

Bus Control

4 I/O Ports

8 8 8 8
P0 P2 P1 P3

TxD RxD

Address/Data

Registers

8-bit registers General purpose: R0, R1, ... R7 Special function: A, B, PSW, SP, I/O ports(p0,p1,p2,p3),scon,ie,ip,tcon,tmod..

16-bit registers DPTR (=DPH, DPL)

PC is not an addressable register though

8051 architecture contains the following:

8 bit CPU with registers A and B 16 bit program counter(PC) and data pointer(DPTR) 8 bit program status word(PSW) 8 bit stack pointer Internal ROM of 0(8031) to 4K(8051) Internal RAM of 128 Bytes 4 register banks 00-1f 16 bytes(bit addressable) 20-2f 80 bytes of general purpose data memory 30-7f

 32 I/O pins arranged as four 8 bit ports (P0 P3) 2 16-bit timer/counters: T0 and T1 Full duplex serial data receiver/transmitter: SBUF Control registers: TCON, TMOD, SCON, PCON, IP and IE 2 external and 3 internal interrupt sources Oscillator and clock circuits

P3.0: RXD Serial asynchronous communication input or Serial synchronous communication output.
P3.1: TXD Serial asynchronous communication output or Serial synchronous communication clock output. P3.2: INT0 Interrupt 0 input. P3.3: INT1 Interrupt 1 input.

P3.4: T0 Counter 0 clock input.

P3.5: T1 Counter 1 clock input. P3.6: WR Write to external (additional) RAM. P3.7: RD Read from external RAM

8051 memory
8051 implements a separate memory space for programs (code) and data. Both code and data may be internal, however, both expand using external components to a maximum of 64K code memory and 64K data memory. Internal memory consists of on-chip ROM and on-chip data RAM Memory capacities : Internal RAM-128 Bytes Internal ROM-4 K Bytes External RAM-64 K Bytes External ROM-64 K Bytes

FFFFH

FFFFH
PSEN

EXTERNAL RAM SFR 80H memory 7FH INTERNAL RAM 00H FFH 0FFFH INTERNNAL ROM

EXTERNAL ROM

0000H

0000H

0000H

EA

External ROM is accessed whenever the EA(external access) pin is connected to ground.

Port 0 is time multiplexed (lower-order byte of 16-bit address and data).

Port 2 provides the high byte of memory address. PSEN (program store enable) pin must be connected to output enable pin of code memory.

8051 Addressing Modes

Register addressing Immediate addressing Direct addressing Indirect addressing

Addressing mode = way of specifying operand

An instruction consists of Opcode (e.g., ADD, MOV, ...) Operand(s)(e.g., R3, #23H, ...) Where is the (value of) operand located? part of the instruction (immediate) in data memory (direct, indirect, indexed) in register; also, in a bit of a register/pin

Immediate addressing mode

Data is part of the instruction.

Register addressing mode

Register is part of the instruction

Some Simple Instructions

MOV dest,source ; dest <= source
MOV A,#72H ;A=72H MOV R4,#62H ;R4=62H MOV B,0F9H ;B=the content of F9th byte of RAM MOV DPTR,#7634H MOV DPL,#34H MOV DPH,#76H

MOV P1,A

;move A to port 1

Note 1:
MOV A,#72H MOV A,72H After instruction MOV A,72H the content of 72th byte of RAM will replace in Accumulator.

Note 2:
MOV A,R3 MOV A,3

ADD A, Source
ADD A,#6 ADD A,R6

;A<=A+SOURCE
;A<=A+6 ;A<=A+R6

ADD A,6
ADD A,0F3H

;A<=A+[6] or A<=A+R6
;A<=A+[0F3H]

SUBB
SUBB

A, Source
A,#6

;A<=A-SOURCE-C
;A=A-6-c

SUBB

A,R6

;A=A+R6-c

MUL & DIV

MUL MOV MOV MUL
DIV MOV MOV DIV

AB ;B:A = A*B A,#25H B,#65H AB ;25H*65H=0E99H ;B=0EH, A=99H

AB ;A = A/B, B = A mod B A,#25 B,#10 AB ;A=2, B=5

SETB bit CLR bit

SETB SETB SETB SETB SETB C P0.0 P3.7 ACC.2 05

; bit=1 ; bit=0
; CY=1 ;bit 0 from port 0 =1 ;bit 7 from port 3 =1 ;bit 2 from ACCUMULATOR =1 ;set high D5 of RAM loc. 20h

CLR CLR

C A

;CY=0, bit operation ;A=0 , byte operation

DEC INC
INC DEC DEC

byte byte
R7 A 40H

;byte=byte-1 ;byte=byte+1

; [40]=[40]-1

RR RL RRC RLC A
EXAMPLE: RR A RR: RRC: RL: RLC:
C
C

ANL - ORL XRL Bitwise Logical Operations: AND, OR, XOR

EXAMPLE: MOV R5,#89H ANL R5,#08H

CPL
Example: MOV L01: CPL MOV ACALL SJMP

;1s complement
A,#55H ;A=01010101 B A P1,A DELAY L01

Stack in the 8051

The register used to access the stack is called SP (stack pointer) register. The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.
7FH Scratch pad RAM 30H 2FH

Bit-Addressable RAM
20H 1FH 18H 17H 10H 0FH 08H 07H 00H

Register Bank 3 Register Bank 2 (Stack) Register Bank 1 Register Bank 0

Example: MOV MOV MOV PUSH PUSH PUSH R6,#25H R1,#12H R4,#0F3H 6 1 4

0BH 0AH 09H 08H Start SP=07H

0BH 0AH 09H 08H 25

0BH 0AH 09H 08H 12 25

0BH 0AH 09H 08H F3 12 25

SP=08H

SP=09H

SP=08H

LOOP and JUMP Instructions

Conditional Jumps :
JZ
JNZ DJNZ

Jump if A=0
Jump if A/=0 Decrement and jump if A/=0

CJNE A,byte
CJNE reg,#data JC JNC JB JNB JBC

Jump if A/=byte
Jump if byte/=#data Jump if CY=1 Jump if CY=0 Jump if bit=1 Jump if bit=0 Jump if bit=1 and clear bit

DJNZ:
Write a program to clear ACC, then add 3 to the accumulator ten times Solution: MOV MOV ADD DJNZ MOV A,#0 R2,#10 A,#03 R2,AGAIN ;repeat until R2=0 (10 times) R5,A

AGAIN:

LJMP(long jump) LJMP is an unconditional jump. It is a 3-byte instruction. It allows a jump to any memory location from 0000 to FFFFH. AJMP(absolute jump) In this 2-byte instruction, It allows a jump to any memory location within the 2k block of program memory. SJMP(short jump) In this 2-byte instruction. The relative address range of 00FFH is divided into forward and backward jumps, that is , within -128 to +127 bytes of memory relative to the address of the current PC.

CALL Instructions
Another control transfer instruction is the CALL instruction, which is used to call a subroutine.

LCALL(long call) This 3-byte instruction can be used to call subroutines located anywhere within the 64K byte address space of the 8051. ACALL (absolute call) ACALL is 2-byte instruction. the target address of the subroutine must be within 2K byte range.

Example: Write a program to copy a block of 10 bytes from RAM location starting at 37h to RAM location starting at 59h. Solution: MOV R0,#37h MOV R1,#59h MOV R2,#10 L1: MOV A,@R0 MOV @R1,A INC R0 INC R1 DJNZ R2,L1

; source pointer ; dest pointer ; counter

8051 timer/counter

Timers /Counters Programming

The 8051 has 2 timers
timer 0 Timer 1

They can be also used as counters 1. The timer is used as a time delay generator.

The clock source is the internal crystal frequency of the 8051.

External input from input pin to count the number of events on registers. These clock pulses could represent the number of people passing through an entrance, or the number of wheel rotations, or any other event that can be converted to pulses.

2. An event counter.

Timer usage
Set the initial value of registers Start the timer and then the 8051 counts up. Input from internal system clock (machine cycle) When the registers equal to 0 and the 8051 sets a bit to denote time out
8051

P2 Set Timer 0

P1 TH0 TL0

to LCD

Counter usage
Count the number of events
Show the number of events on registers External input from T0 input pin (P3.4) for Counter 0 External input from T1 input pin (P3.5) for Counter 1 External input from Tx input pin. We use Tx to denote T0 or T1.
8051
TH0 P1

TL0
P3.4 a switch T0

to LCD

Registers Used in Timer/Counter

TH0, TL0, TH1, TL1 TMOD (Timer mode register) TCON (Timer control register)

TMOD Register
Timer mode register: TMOD
MOV TMOD,#21H An 8-bit register Set the usage mode for two timers Set lower 4 bits for Timer 0 (Set to 0000 if not used) Set upper 4 bits for Timer 1 (Set to 0000 if not used) Not bit-addressable

(MSB) GATE C/T M1 Timer 1

M0 GATE C/T M1 Timer 0

(LSB) M0

 Every timer has a mean of starting and stopping.

GATE=0 Internal control The start and stop of the timer are controlled by way of software. Set/clear the TR for start/stop timer. SETB TR0 CLR TR0 GATE=1 External control The hardware way of starting and stopping the timer by software and an external source. Timer/counter is enabled only while the INT pin is high and the TR control pin is set (TR).

Gate

(MSB) GATE C/T M1 Timer 1

M0 GATE C/T M1 Timer 0

(LSB) M0

Figure 9-3. TMOD Register

C/T Timer or counter selected cleared for timer operation (input from internal system clock). Set for counter operation (input from Tx input pin).

M1 M0 Mode Operating Mode 0 0 0 13-bit timer mode 8-bit THx + 5-bit TLx (x= 0 or 1) 0 1 1 16-bit timer mode 8-bit THx + 8-bit TLx 1 0 2 8-bit auto reload 8-bit auto reload timer/counter; THx holds a value which is to be reloaded into TLx each time it overflows. 1 1 3 Split timer mode

(MSB) GATE C/T M1 Timer 1 M0 GATE C/T M1 Timer 0

(LSB) M0

Timer modes

TCON Register (1/2)

Timer control register: TMOD
Upper nibble for timer/counter, lower nibble for interrupts

TR (run control bit)

TR0 for Timer/counter 0; TR1 for Timer/counter 1. TR is set by programmer to turn timer/counter on/off. (MSB) TF1 TR1 Timer 1
TR=0: off (stop) TR=1: on (start)

TF0 TR0 Timer0

IE1

IT1 IE0 for Interrupt

(LSB) IT0

TCON Register (2/2)

TF (timer flag, control flag)
TF0 for timer/counter 0; TF1 for timer/counter 1. TF is like a carry. Originally, TF=0. When TH-TL roll over to 0000 from FFFFH, the TF is set to 1.
TF=0 : not reach TF=1: reach If we enable interrupt, TF=1 will trigger ISR.

(MSB) TF1 TR1 Timer 1

TF0 TR0 Timer0

IE1

IT1 IE0 for Interrupt

(LSB) IT0

Equivalent Instructions for the Timer Control Register

For timer 0 SETB TR0 CLR TR0 SETB TF0 CLR TF0 For timer 1 SETB TR1 CLR TR1 SETB TF1 CLR TF1 = = = = SETB TCON.6 CLR TCON.6 SETB TCON.7 CLR TCON.7 = = = = SETB TCON.4 CLR TCON.4 SETB TCON.5 CLR TCON.5

TCON: Timer/Counter Control Register

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Steps of Mode 1 (1/3)

1. Choose mode 1 timer 0
MOV TMOD,#01H

2. Set the original value to TH0 and TL0.

MOV TH0,#FFH MOV TL0,#FCH

3. You had better to clear the flag to monitor: TF0=0.

CLR TF0

4. Start the timer.

SETB TR0

Steps of Mode 1 (2/3)

5.The 8051 starts to count up by incrementing the TH0-TL0.
TH0-TL0= TR0=1 FFFCH,FFFDH,FFFEH,FFFFH,0000H
Start timer TH0 TL0 FFFE TR0=0

Stop timer

FFFC

FFFD

FFFF

0000

TF = 0

TF = 0 TF

TF = 0 Monitor TF until TF=1

TF = 0

TF = 1

Steps of Mode 1 (3/3)

6. When TH0-TL0 rolls over from FFFFH to 0000, the 8051 set TF0=1.
TH0-TL0= FFFEH, FFFFH, 0000H (Now TF0=1)

7. Keep monitoring the timer flag (TF) to see if it is raised.

AGAIN: CLR TR0 JNB TF0, AGAIN

8. Clear TR0 to stop the process.

9. Clear the TF flag for the next round.

CLR TF0

8051 Interrupts

Interrupts Programming
An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service. The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler.

Steps in executing an interrupt

Finish current instruction and saves the PC on stack.
Jumps to a fixed location in memory depend on type of interrupt Starts to execute the interrupt service routine until RETI (return from interrupt)

Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get pop PC from stack

Interrupt Sources
Original 8051 has 6 sources of interrupts
Reset Timer 0 overflow Timer 1 overflow External Interrupt 0 External Interrupt 1 Serial Port events (buffer full, buffer empty, etc)

Interrupt Vectors
Each interrupt has a specific place in code memory where execution of interrupt service routine begins.
External Interrupt 0: Timer 0 overflow: External Interrupt 1: Timer 1 overflow: Serial : Timer 2 overflow(8052+) 0003h 000Bh 0013h 001Bh 0023h 002bh

Note: that there are only 8 memory locations between vectors.

Interrupt Enable (IE) register

All interrupt are disabled after reset We can enable and disable them bye IE

Enabling and disabling an interrupt

by bit operation Recommended in the middle of program SETB EA SETB IE.7 SETB ET0 SETB IE.1 SETB ET1 SETB IE.3 SETB EX0 SETB IE.0 SETB EX1 SETB IE.2 SETB ES SETB IE.4

;Enable ;Enable ;Enable ;Enable ;Enable ;Enable

All Timer0 ovrf Timer1 ovrf INT0 INT1 Serial port

by mov instruction Recommended in the first of program

MOV IE, #10010110B

Example
A 10khz square wave with 50% duty cycle
ORG LJMP ORG T0ISR:CPL RETI 0 MAIN 000BH P1.0
;Reset entry point ;Jump above interrupt ;Timer 0 interrupt vector ;Toggle port bit ;Return from ISR to Main program

ORG 0030H MAIN: MOV TMOD,#02H MOV TH0,#50 SETB TR0 MOV IE,#82H SJMP $ END

;Main Program entry point ;Timer 0, mode 2 ;50 us delay ;Start timer ;Enable timer 0 interrupt ;Do nothing just wait

External interrupt type control

By low nibble of Timer control register TCON IE0 (IE1): External interrupt 0(1) edge flag.
set by CPU when external interrupt edge (H-to-L) is detected.
Does not affected by H-to-L while ISR is executed(no int on int) Cleared by CPU when RETI executed. does not latch low-level triggered interrupt

IT0 (IT1): interrupt 0 (1) type control bit.

Set/cleared by software IT=1 edge trigger IT=0 low-level trigger

(MSB) TF1 TR1 Timer 1

TF0 TR0 Timer0

IE1

IT1 IE0 for Interrupt

(LSB) IT0

External Interrupts
Level-triggered (default) INT0 (Pin 3.2) 0 1 2 IT0 IE0 (TCON.3) 0003

Edge-triggered

Level-triggered (default) INT0 (Pin 3.3) 0 1 2 IT1 IE1 (TCON.3) 0013

Edge-triggered

Interrupt Priorities
What if two interrupt sources interrupt at the same time? The interrupt with the highest PRIORITY gets serviced first. All interrupts have a power on default priority order.
1. External interrupt 0 (INT0) 2. Timer interrupt0 (TF0) 3. External interrupt 1 (INT1) 4. Timer interrupt1 (TF1) 5. Serial communication (RI+TI)

Priority can also be set to high or low by IP reg.

Interrupt Priorities (IP) Register

----PT2 PS PT1 PX1 PT0 PX0

IP.7: reserved IP.6: reserved IP.5: timer 2 interrupt priority bit(8052 only) IP.4: serial port interrupt priority bit IP.3: timer 1 interrupt priority bit IP.2: external interrupt 1 priority bit IP.1: timer 0 interrupt priority bit IP.0: external interrupt 0 priority bit

Interrupt Priorities Example

-- --PT2 PS PT1 PX1 PT0 PX0

MOV IP , #00000100B or SETB IP.2 gives priority order

1. 2. 3. 4. 5. Int1 Int0 Timer0 Timer1 Serial Int1 Timer1 Int0 Timer0 Serial

MOV IP , #00001100B gives priority order

1. 2. 3. 4. 5.

Interrupt inside an interrupt

--

---

PT2

PS

PT1

PX1

PT0

PX0

A high-priority interrupt can interrupt a low-priority interrupy All interrupt are latched internally Low-priority interrupt wait until 8051 has finished servicing the high-priority interrupt

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