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Background for

Leakage Current
Sept. 18, 2006
Power Challenge
Active power density increasing with
device scaling and increased frequency
Leakage power density increasing due
to lower Vt and gate leakage
Stressing packaging, cooling, battery
life, etc.
Complicates IDDq testing as well

Thinning gate oxides
increase
gate tunneling leakage
Source from Bergamaschi
Problem Statement
Power Analysis on CMOS Inverter
Input switching to '1' or '0'
charge
discharge
Input
Cload
Vthn< Input < VDD-|Vthp|
Input
Input : '1' or '0' steady state
Input
(a) Capacitive Current (b) Short Circuit Current (c) Static Leakage Current
Problem Statement
Dynamic Power

Average Short Circuit Current



Sub-threshold Leakage Current
P C VDD f
switching switching
=
2
I
VDD
VDD V f
SC
in
th
=


| t
12
2
3
( )
gain factor
Threshold Voltage V V V
n p
thn thp th
_ : ,
_ :
| | | = =
= =
I e e
DS
V V q nkT V q kT
GS th DS
=

K
( ) / /
( ) 1
K V V
V q k T
n kT
GS DS
th
: : , :
: : , : :
: ~ ( . )
function of technology, gate to source voltage drain to source voltage,
theshold voltage, electronic charge Boltzmann constance, temperature,
nonlinearity constance ,

~ 1 2 0 0259
Problem Statement
Domination of Leakage Current
Feature Size
Core Voltage
V
TH
(Threshold)
Performance(AP)
TR Leakage
Stand-by Mode
Low Power
> 0.25um
5.0/3.3/2.5V
> +/- 0.6V
< 200MHz
Negligible
PLL-off(Clock-off)
Focus on Operating Power
0.18/0.13/0.09um
1.8/1.2/1.0V
+/- 0.5, 0.4, 0.3V
300/400/533MHz, 1GHz
Exponential growing(SD/Gate)
V/MTMOS, High V
TH
/High VDD
Focus on Operating/Stand-by
Active and Leakage Power with CMOS
Scaling
As CMOS scales down the
following stand-by leakage
current rises rapidly.
Source to drain leakage
(diffusion+tunneling) as
Lg scales down
Gate leakage current
(tunneling) as Tox scales
down
Body to drain leakage
current (tunneling) as
channel doping scales
up

Two cases of Leakage Mechanism
Vg=0V Turn off
Vd=Vdd
Turn on
Vg=Vdd
Vd=0V
Sub-threshold Leakage
Source to drain tunneling
Drain to Body tunneling (BTB)
Gate oxide
tunneling
Gate Leakage Current Reduction with
High-K Gate Dielectric
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
20 25 30 35 40
C
u
r
r
e
n
t

D
e
n
s
i
t
y

(
A
/
c
m

2
)

Tox (A)
Gate leakage
Drain leakage
C
k A
T
ox
physical
=
c
0
High-K gate dielectric
Voltage Scaling for Low Power
Low Power
Low VDD
Low Speed
Speed Up
Low V
th

P VDD
2

I
ds
(VDD - V
th
)
1~2
I
ds
(VDD - V
th
)
1~2

High Leakage
I
leakage
e
-C x Vth

Leakage
Suppression
Low-Leakage Solution Technology
D
y
n
a
m
i
c

p
o
w
e
r
[
W
]

Leakage power[W]
V
TH
: 0.5V V
TH
: 0.25V
High speed
Low speed Low speed
VDD control
V
TH
control
High speed
MTCMOS
VDD: 1.5V
VDD: 1.0V
VDD control
V
TH
control
100n
1
10
100
100p 1p 10p 100n 1n 10n
VTCMOS & MTCMOS
Multi-Threshold CMOS Variable-Threshold CMOS
S
c
h
e
m
a
t
i
c

D
i
a
g
r
a
m

p
r
i
n
c
i
p
l
e

On-off control of internal
VDD or VSS
Special F/Fs, Two Vths
Threshold control with bulk-bias
Triple well is desirable
Low leakage in stand-by mode.
Conventional design Env.
M
e
r
i
t

Low leakage in stand-by mode.
Conventional design Env.
D
e
m
e
r
i
t

Large serial MOSFET
ground bounce noise
Ultra-low voltage region?(1V)
Scalability? (junction leakage)
TR reliability under 0.1m
Latch-up immunity, Vth controllability,
Substrate noise, Gate oxide reliability
Gate leakage current
Low- Vth
VDD
GND
Hi- Vth Sleep
Low Vt
VDD
GND
Vt
Control
circuit
Vnb = 0 or V-
Vpb = VDD
or V+
N-well
P-well
MTCMOS : Reduce Stand-by Power with
High Speed
With High V
TH
switch, much lower leakage current flows
between Vdd and Vss
High V
TH
MOSFET should have much lower ( >10X) leakage
current compared to normal V
TH
MOSFET
Vdd
Vss
0
0
Vdd
Vss
1
1
0
Without High V
TH
switch
With High V
TH
switch (MTCMOS)
High V
TH
switch
Normal or Low V
TH
MOSFET
Virtual Ground
Multi-Threshold CMOS (MTCMOS)
Mobile Applications
Mostly in the idle state
Sub-threshold leakage Current
Power Gating
Low V
TH
Transistors for High Performance Logic
Gates
High V
TH
Transistors for Low Leakage Current
Gates

Active Sleep Active
Sleep
Control
(SC)
Time
Operating
Mode
Current
Cutoff-Switch
(High V
th
)
SC
VDD
VSS
VGND
Low V
th

MOS
High V
th

MOS
Logic
Component
(Low V
th
)
CCS Sizing
The effect of CCS size
As the size decreases, logic performance also
decreases.
As the size increases, leakage current and chip
area also increase.
Proper sizing is very important.
CCS size should be decided within 2%
performance degradation.

Vop = VDD - AV
AV must be sized
within 2% performance degradation.
VDD
GND
Low Vt
High Vt
Switch
Control
Leakage Current :
Limiting Factor in VDSM
Technology

C.M.Kyung
ITRS roadmap
Scaling down allows the same performance with
reduced voltage, leading to low power.
From 0.18 micron down, building a transistor with a
good active current(I
on
) and a low leakage current (I
off
)
is difficult.
high-speed TRs ; low channel doping
low-leakage TRs ; high channel doping
Now three groups of TRs;
High Performance (HP) ; high active current ; Thin T
ox

Low Operating Power (LOP) ; low active current ; High T
ox
Low Standby Power (LSTP) ; low static current ; High T
ox
Device characteristics for HP,
LOP, and LSTP Technologies
Table 2.1
Bulk CMOS vs. SOI
Buried oxide layer below active silicon
layer -> electrical isolation of TRs
Lower parasitic cap.
PD(Partially Depleted)
Floating body effect increases speed
Low threshold in dynamic mode
or FD(Fully Depl)
Ideal subthresold swing of 60 mV/decade

Reducing Subthreshold current in
Bulk CMOS
VTCMOS (Variable Threshold)
Tune substrate bias to adjust V
th
Requires efficient DC-DC converter
For a given technology, there an optimum in V
R
, as
decreasing subthreshold leakage is accompanied by an
increase in drain junction leakage
When both High Vt and Low Vt TRs are available,
MTCMOS (Multi-Threshold) ; Introduce high Vt power switch
to limit leakage in stby mode
Use low Vt for critical path
This can be coupled with multiple VDDs
Other tricks
Set up the logical internal states where the total leakage is
minimal.
Five types of off-currents
Tunneling through gate oxide
Fowler-Nordheim tunneling -> direct tunneling
Subthreshold current
Gate-induced drain leakage (GIDL)
Thermal emission
Trap-assisted tunneling
BTBT
Reverse-biased pn junction current
-> band-to-band tunneling (BTBT) current
Bulk punch-through

Gate-induced drain leakage
(GIDL)
Gate-induced drain leakage (GIDL)
Thermal emission
Trap-assisted tunneling
BTBT
Fig 3.12
Leakage current due to
QM Tunneling
substrate and drain ; band-to-band
tunneling ;
increases with E-field and dopant concentration
due to scaling
source and drain ;
Surface punchthru due to DIBL
Punch-through at bulk
gate oxide ;
SiO2 has been used as it has so low trap and
fixed charge density at the interface
Gate current is an exponential function of Tox and
Vox
Hole tunneling is 10% of that of electron due to
higher barrier height and heavier effective mass

Gate Leakage Current Reduction with
High-K Gate Dielectric
As Tox scales gate leakage current increases
exponentially due to exponential increase of
tunneling probability with reduction of physical
tunneling distance.
Physically thicker gate dielectric allows lower
leakage current but lower oxide capacitance
reducing on-current
Using high k (dielectric constant) material, both
thicker physical thickness and higher oxide
capacitance can be achieved.
Applying high-k gate dielectric, several orders of
magnitude lower gate leakage current can be
achieved with similar oxide capacitance

Approach 1 to reduce gate
leakage ; High K materials
To suppress gate tunneling current, use
materials with
High K -> increases thickness (t)
Higher barrier height (h)
Using high K
Increases short-channel effects due to thicker
gate dielectric (This sets an upper limit on K, lower
limit coming from I tunnel)
Mobility degradation due to poor interface quality

Approach 2 to reduce gate leakage ; stop
scaling the thickness of gate oxide
Thicker gate oxide yields less control of
gate on channel conduction, i.e., higher
short-channel effects and DIBL effects.
Approach 3 to reduce gate leakage
Multiple gates allows better control of
channel by gate, and lets scaling continue
without excessive short-channel effects
Double gate
FinFET
Triple gate
Quadruple or gate all-around

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