EE415 VLSI Design

1
The Wire
[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]
EE415 VLSI Design
2
The Wire
transmitters
receivers
schematics
physical
EE415 VLSI Design
3
Interconnect Impact on Chip

EE415 VLSI Design
4
Wire Models
All-inclusive model
Capacitance-only
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5
Impact of Interconnect Parasitics
Interconnect parasitics
reduce reliability
affect performance and power
consumption
Classes of parasitics
Capacitive
Resistive
Inductive
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6
10 100 1,000 10,000 100,000
Length (u)
N
o

o
f

n
e
t
s
(
L
o
g

S
c
a
l
e
)
Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
Nature of Interconnect
Local Interconnect
Global Interconnect
S
Local
= S
Technology
S
Global
= S
Die
S
o
u
r
c
e
:

I
n
t
e
l

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INTERCONNECT
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Wiring Capacitance
The wiring capacitance depends upon the
length and width of the connecting wires and is
a function of the fan-out from the driving gate
and the number of fan-out gates.
Wiring capacitance is growing in importance
with the scaling of technology.
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9
Capacitance of Wire Interconnect
V
DD
V
DD
V
in
V
out
M1
M2
M3
M4
C
db2
C
db1
C
gd12
C
w
C
g4
C
g3
V
out2
Fanout
Interconnect
V
out
V
in
C
L
Simplified
Model
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10
Capacitance: The Parallel Plate Model
Dielectric
Substrat e
L
W
H
t
di
Electrical-field lines
Current flow
WL
t
c
di
di
int
c
=
L L
Cwire
S S S
S
S
1
=

=
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Permittivity Values of Some Dielectrics
3.1 3.4 Polyimides (organic)
2.1 Teflon AF
11.7 Silicon
9.5 Alumina (package)
7.5 Silicon nitride
5 Glass epoxy (PCBs)
3.9 4.5 Silicon dioxide
2.6 2.8 Aromatic thermosets (SiLK)
1.5 Acrogels
1 Free space
c
di
Material
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Fringing Capacitance
W - H/2 H
+
(a)
(b)
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Fringing versus Parallel Plate
(from [Bakoglu89])
H/T
H/T
W/T
H
T
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Sources of Interwire Capacitance
C
wire
= C
pp
+ C
fringe
+ C
interwire

= (c
di
/t
di
)WL
+ (2tc
di
)/log(t
di
/H)
+ (c
di
/t
di
)HL
interwire
fringe
pp
W
W
W
H
H
H
t
di
t
di
t
di
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Impact of Interwire Capacitance
(from [Bakoglu89])
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Wiring Capacitances
Field Active Poly Al1 Al2 Al3 Al4
Poly 88
54
Al1 30 41 57
40 47 54
Al2 13 15 17 36
25 27 29 45
Al3 8.9 9.4 10 15 41
18 19 20 27 49
Al4 6.5 6.8 7 8.9 15 35
14 15 15 18 27 45
Al5 5.2 5.4 5.4 6.6 9.1 14 38
12 12 12 14 19 27 52
fringe in aF/m
par. plate in aF/m
2
Poly Al1 Al2 Al3 Al4 Al5
Interwire Cap 40 95 85 85 85 115
per unit wire length in aF/m for minimally-spaced wires
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Dealing with Capacitance
Low capacitance (low-k) dielectrics
(insulators) such as polymide or even air
instead of SiO
2
family of materials that are low-k dielectrics
must also be suitable thermally and mechanically
and
compatible with (copper) interconnect
Copper interconnect allows wires to be thinner
without increasing their resistance, thereby
decreasing interwire capacitance
SOI (silicon on insulator) to reduce junction
capacitance
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INTERCONNECT
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Wire Resistance
L
W
H
R =
L
H W
Sheet Resistance R

R
1
R
2
=

=

L
A
=
Material (O-m)
Silver (Ag) 1.6 x 10
-8
Copper (Cu) 1.7 x 10
-8
Gold (Au) 2.2 x 10
-8
Aluminum (Al) 2.7 x 10
-8
Tungsten (W) 5.5 x 10
-8
Material Sheet Res. (O/)
n, p well diffusion 1000 to 1500
n+, p+ diffusion 50 to 150
n+, p+ diffusion
with silicide
3 to 5
polysilicon 150 to 200
polysilicon with
silicide
4 to 5
Aluminum 0.05 to 0.1
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Sources of Resistance
MOS structure resistance - R
on

Source and drain resistance
Contact (via) resistance
Wiring resistance
Top view
Drain n+ Source n+
W
L

Poly Gate
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Contact Resistance
Vias add extra resistance to a wire
keep signals wires on a single layer if possible
avoid excess contacts
using multiple vias to make the contact
Typical contact resistances, R
C
,
5 to 20 O for metal or poly to n+, p+ diffusion
and metal to poly
2 to 20 O for metal to metal contacts
More pronounced with scaling since contact
openings are smaller
EE415 VLSI Design
14: Wires 22
Contacts Resistance
Use many contacts for lower R
Many small contacts for current crowding
around periphery
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Skin Effect
At high frequency, currents tend to flow on the surface of a
conductor with the current density falling off exponentially with
depth into the wire
H
W
o= \(/(tf))
where f is frequency
= 4t x 10
-7
H/m

so the overall cross section is ~ 2(W+H)o
o= 2.6 m
for Al at 1 GHz
The onset of skin effect is at f
s
- where the skin depth is equal to half
the largest dimension of the wire.
f
s
= 4 / (t (max(W,H))
2
)
An issue for high frequency, wide (tall) wires (i.e., clocks!)
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Skin Effect for Different Ws
A 30% increase in resistance is observe for 20 m Al wires at 1 GHz
(versus only a 1% increase for 1 m wires)
0.1
1
10
100
1000
Frequency (Hz)
%

I
n
c
r
e
a
s
e

i
n

R
e
s
i
s
t
a
n
c
e
W = 1 um
W = 10 um
W = 20 um
1E8 1E9 1E10
for H = .70 um
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Dealing with Resistance
Selective Technology Scaling
Use Better Interconnect Materials
e.g. copper, silicides
More Interconnect Layers
reduce average wire-length
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Polycide Gate MOSFET
n
+
n
+
SiO
2
PolySilicon
Silicide
p
Silicides: WSi
2,
TiSi
2
, PtSi
2
and TaSi
Conductivity: 8-10 times better than Poly
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Modern Interconnect
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Example: Intel 0.25 micron Process
5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon dielectric
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Interconnect
Modeling
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The Lumped Model
V
out
Driver
c
wi re
V
in
C
lumped
R
driver
V
out
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The Lumped RC-Model
The Elmore Delay
To model propagation delay
time along a path from the
source s to destination i
considering the loading effect
of the other nodes on the path
from s to k

The shared path resistance R
ik




The Elmore delay
s
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The Ellmore Delay
RC Chain
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Wire Model
Assume: Wire modeled by N equal-length segments
For large values of N:
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The Distributed RC-line
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Step-response of RC wire as a
function of time and space
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
0.5
1
1.5
2
2.5
time (nsec)
v
o
l
t
a
g
e

(
V
)
x= L/10
x = L/4
x = L/2
x= L
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RC-Models
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Driving an RC-line
V
in
R
s
V
out
(r
w
,c
w
,L)
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Design Rules of Thumb
rc delays should only be considered when
t
pRC
>> t
pgate
of the driving gate
L
crit
>> \ t
pgate
/0.38rc
rc delays should only be considered when the
rise (fall) time at the line input is smaller than
RC, the rise (fall) time of the line
t
rise
< RC
otherwise, the change in the input signal is slower
than the propagation delay of the wire