CMOS Manufacturing Process

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

CMOS Process

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

CMOS Inverter Layout

GND In VD D A A

Out (a) Layout

A p-substrate n
+

A n p
+

Field Oxide

(b) Cross-Section along A-A

Elettronica D. AA 2000-2001 Manufacturing Process Digital Integrated Circuits Prentice Hall 1995

Patterning on Si

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Semiconductor fabrication (1)

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Semiconductor Fabrication (2)

1

4
Elettronica D. AA 2000-2001 Manufacturing Process Digital Integrated Circuits Prentice Hall 1995

Semiconductor Fabrication (3)

3
Elettronica D. AA 2000-2001 Manufacturing Process

3
Digital Integrated Circuits Prentice Hall 1995

Semiconductor Fabrication (4)

4

END
Elettronica D. AA 2000-2001 Manufacturing Process Digital Integrated Circuits Prentice Hall 1995

Circuit Under Design

VDD M2 M4 Vin Vout Vout2 VDD

M1

M3

Elettronica D. AA 2000-2001

This two-inverter circuit (of Figure 3.25 in the text) will be manufactured in a twin-well process.
Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Circuit Layout
pMOS-1

B2 S2 G2 D2

B4 S4 G4

Vdd
pMOS-2 IN2=OUT1

Inverter 1
nMOS-1 pMOS-1

D4
IN2 OUT2

Inverter 2
nMOS-2 pMOS-2

IN1

OUT1

Inverter 1

D1 G1 S1

D3 G3 S3 B3

Inverter 2

nMOS-1

B1

GND

nMOS-2

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Start Material
A

pMOS

nMOS
A A A

Starting wafer: n-type with

13 3

doping level = 10

/cm

* Cross-sections will be shown along vertical line

Si n-type
Elettronica D. AA 2000-2001 Manufacturing Process

A-A

Digital Integrated Circuits Prentice Hall 1995

N-well Construction
pMOS
(1) Oxidize wafer (2) Deposit silicon nitride (3) Deposit photoresist

nMOS

photoresist

Si n-type
Elettronica D. AA 2000-2001 Manufacturing Process

silicon nitride silicon dioxide

Digital Integrated Circuits Prentice Hall 1995

N-well Construction
pMOS

nMOS

(4) Expose resist using n-well mask

Exposed resist

Si n type
Elettronica D. AA 2000-2001 Manufacturing Process Digital Integrated Circuits Prentice Hall 1995

N-well Construction
pMOS

nMOS

(5) Develop resist (6) Etch nitride and (7) Grow thick oxide

Si n type
Elettronica D. AA 2000-2001 Manufacturing Process Digital Integrated Circuits Prentice Hall 1995

N-well Construction
pMOS
(8) Implant n-dopants

nMOS

(phosphorus) (up to 1.5 mm deep)

thick oxide

n-well Si n type
Elettronica D. AA 2000-2001 Manufacturing Process Digital Integrated Circuits Prentice Hall 1995

P-well Construction
pMOS

nMOS

Repeat previous steps

pMOS
n-well Si n type
Elettronica D. AA 2000-2001

nMOS
p-well

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Grow Gate Oxide

pMOS

nMOS
Gate oxide 55 nm thin

pMOS
n-well Si n type
Elettronica D. AA 2000-2001

nMOS
p-well

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Grow Thick Field Oxide

pMOS
Field Oxide 0.9 mm thick

nMOS
Uses Active Area mask

pMOS
n-well Si n type
Elettronica D. AA 2000-2001

nMOS
p-well

Is followed by threshold-adjusting implants

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Polysilicon layer
pMOS
Polysilicon Deposition

nMOS pMOS
n-well Si n type
Elettronica D. AA 2000-2001 Manufacturing Process Digital Integrated Circuits Prentice Hall 1995

nMOS p-well

Source-Drain Implants
pMOS
photoresist
n+ source-drain implant (using n+ select mask)

nMOS

pMOS
n-well Si n type
Elettronica D. AA 2000-2001

nMOS p-well
n+ source-drain implant (using n+ select mask)
Digital Integrated Circuits Prentice Hall 1995

Manufacturing Process

Source-Drain Implants
pMOS
p+ source-drain implant (using p+ select mask)

nMOS pMOS
B S G D D

nMOS
G S B

n-well Si n type
Elettronica D. AA 2000-2001 Manufacturing Process

p-well

Digital Integrated Circuits Prentice Hall 1995

Contact-Hole Definition
pMOS
(1) Deposit inter-level Dielectric (SiO2) 0.75 mm (2) Define contact opening using contact mask

nMOS

pMOS
n-well Si n type
Elettronica D. AA 2000-2001

nMOS p-well

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Aluminum-1 Layer
pMOS
Aluminum evaporated (0.8 mm thick) IN

OUT
followed by other metal layers and glass

nMOS
Vdd B S G D G
IN

GND D G S B

OUT

pMOS
Elettronica D. AA 2000-2001

nMOS
Manufacturing Process Digital Integrated Circuits Prentice Hall 1995

Advanced Metalization

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Intel 0.09 mm Generation

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Downsizing MOSFET below 0.1 mm

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Design Rules

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Design Rules

Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

CMOS Process Layers

Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Color Yellow Green Green Red Blue Magenta Black Black Black Representation

Metal1 Metal2
Contact To Poly Contact To Diffusion Via

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Intra-Layer Design Rules

Same Potential Well 10 Active 3 2 Select 3 Contact or Via Hole 2 2 Metal1 3 0 or 6 Different Potential 9 Polysilicon 2 3 2

Metal2 3
Elettronica D. AA 2000-2001 Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Transistor Layout
Transistor

Transistor

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Vias and Contacts

2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

Elettronica D. AA 2000-2001

Manufacturing Process

Digital Integrated Circuits Prentice Hall 1995

Select Layer
2 3 1 3 3 2 Select

Substrate
Elettronica D. AA 2000-2001 Manufacturing Process

Well
Digital Integrated Circuits Prentice Hall 1995