PDP Training (Alexander)

Agenda
1.Explanation of Layout and Function of Circuit Board 2.Operation Explanation per Board
2-1 2-2 2-3 2-4 Drive Description on SMPS Operation Explanation of Driving Circuit Logic-Main Board Scaler Board

1. Explanation of Layout & Function of Circuit Board

[PDP Module Picture]
Y buffer "Upper"

SMPS
Y-MAIN X-MAIN

Logic-Main

Y buffer "Lower"

E-buffer

F-buffer

G-buffer

COF x 7

[ Function Description by board - 1 ]

.SMPS(Switching Mode Power Supply) : It is the supplier to provide voltage and current to work the drive voltage and panel in each board.

.X-MAIN BOARD : It makes the drive wave form by switching FETs to Timing Controlle coming from logic-board and supplies X electrode of panel with the drive wave form via connector.

.Y-MAIN BOARD : It makes the drive wave form by switching FETs to Timing Controller coming from the logic-board and provides Y electrode of panel with the drive wave form via Scan Driver IC on Y buffer board in order.

.LOGIC MAIN BOARD : It process image signal and performs buffering of the logic-main board (to create XY drive signal and output) and the address driver output signal. Then it supplies the output signal to the address driver IC(COF Module).

[ Function Description by board - 2 ]

.LOGIC BUFFER(E,F,G) : It delivers the data signal and control signal to the COF.

.Y-BUFFER (Upper,Lower) : It is the board to impress the scan waveform on the Y board and consist of 2 boards (upper board and lower board). 8 Y-buffers are fixed at the scan driver (STV7617 of STC corp. : 64 or 65 Output).

.AC Noise Filter : It has functions to remove noise(low frequency) coming from AC LINE and prevent surge. It gives serious effects on the safety regulations (EMC, EMI) according to AC filter.

.COF(Chip on Flexible) : It impress the Va pulse to the address electrode in the address section and forms the address discharge by electric potential difference with scanning pulse to be dismissed by the Y electrode. It is made in the form of COF and one COF consists of 4 Data Drive IC (STV7610A :96 Output), otherwise single scan is made of 7 COF.

CELL STRUCTURE OF PDP

Bus electrode Front panel

Dielectric MgO layer

Barrier

ITO electrode Phosphors

Address Electrode

Back panel

Electro Arrangement of SD PDP

A1 Y1 X Y2 X A2 A3 A4 A5 A6 A7

Y480 X

Reference
- A1,A2, , , : Address Electrode - Y1,Y2, , , : Scan & Sustain Electrode - X : Common & Sustain Electrode

ADDRESS OPERATION

In order to display picture,

select the cells.

SUSTAIN OPERATION

Display cells through strong Sustain discharge.

1 SUB-FIELD IMAGE PROCESS (ADS)

Reset

Address

Sustain

Function Sustain Erase Wall Charge Set Issue Operation margin Contrast Short Time

Function Select On Cell Issue High Speed Low Voltage Low Failure

Function Discharge On Cell Issue High Efficiency Low Voltage ERC Performance

FRAME STRUCTURE (ADS)

SF1 scan line
1 2 .. ... 480

SF2

SF3

SF4

SF5

SF6

SF7

SF8 sub-field address

1T 2T 4T 8T 16T

32T

64T

128T

sustain

1TV field (time)

Reset Period Address Period Sustain Period

D X Y1 Y2

Yn

1 Picture Structure by 8 sub-field

SF1 scan line

1 2 .. ... 480

SF2

SF3

SF4

SF5

SF6

SF7

SF8 sub-field address

1T 2T 4T 8T 16T

32T

64T

128T

sustain

1TV field (time)

2. Explanation of Operation per Boards

[Whole Block Diagram]
Y-Main B'd

Logic B'd

Display Data DRAM Driver Timing Row Driver 852 X 480 Pixels 853 X 3 X 480 Cells Y-Pulse Scan Timing Generator Column Driver Power B'd

X-Main B'd

PDP Panel
X-Pulse Generator

Input Data Processor

Data Controller

Driver Timing Controller Clock :

Clock : 27MHz

Clock : 60MHz

20MHz 40MHz

Power Supply

LVDS
Digital B'd Analog B'd Audio Processor Video S/W Comb Filter Tuner

Image Enhancer Image Scalerr Micom AD Converterr

Deinterlacer Video Decoder TMDS Receiverr

AC Power Source 220V

1 Picture Structure by 8 sub-field

[Wiring Diagram Schematic ]

CN805 (10P)

CN805 (10P)

Y-Main

SMPS CN806) CN812 (5P) CN802 CN803 (10P) (11P)

CN804 (9P)

CN804 (9P)

CN801 (10P)

X-Main

LA03 (31P) CN201 CN201 CN401

CN803 (10P)

Logic
CN402

CN101 CN403

CN101

CN806)

EF1

FE1 FG1 CN101 CN102 CN103

GF1 AC Inlet

CN111 CN601

CN802

CN801

Digital

Analog

PIN CONFIGURATION
[ Scaler : Analog Dgital ]
CN101(Control) NO 1 2 3 4 5 6 7 8 9 10 11 12 PIN Name GND SCL1 SDA1 GND SAFT GND MUTE GND MAFT GND ANAL_CVBS GND CN102(Video/Sync) NO 1 2 3 4 5 6 7 8 9 10 11 12 PIN Name ANAL_YCOMB GND ANAL_CCOMB GND ANAL_Y2 GND ANAL_PB2 GND ANAL_PR2 GND ANAL_H ANAL_V CN103(Video/Sync) NO 1 2 3 4 5 6 7 8 9 10 11 12 PIN Name ANAL_YCOMB GND ANAL_CCOMB GND ANAL_Y2 GND ANAL_PB2 GND ANAL_PR2 GND ANAL_H ANAL_V NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14

[ Scaler Dgital Logic (CN601) ]

PIN Name GND GND Tx Out0- / Rx In0Tx Out0+ / Rx In0+ GND GND Tx Out1- / Rx In1Tx Out1+ / Rx In1+ GND GND Tx Out2- / Rx In2Tx Out2+ / Rx In2+ GND GND NO 17 18 19 20 21 22 23 24 25 26 27 28 29 31 PIN Name GND GND Tx Out0- / Rx In0Tx Out0- / Rx In0GND GND GND GND RESET_MN GND IIC SCL2 GND IIC SDA2 GND GND 16 Tx CLK Out+ / Rx CLK In+

15 Tx CLK Out- / Rx CLK In- 30

PIN CONFIGURATION
[ SMPS Analog / Digital / Logic ]
CN801(Analog Tu) NO 1 2 3 4 5 6 7 8 9 10 Power GND A33V GND GND AMP12V AMP12V GND D12V GND D6V CN802(Digital Tu) NO 1 2 3 4 5 6 7 8 9 10 11 Power THEM_D STD_5V GND PS_ON N.C. GND GND D3.3V D3.3V GND D6V 1 2 3 4 5 6 7 8 9 10 CN803(Logic) NO Power D3.3V D3.3V GND GND D5V GND IC2 IC2 PS_ON GND NO 1 2 3 4 5 6 7 8 9

[ SMPS X,Y-Main / Buffer ]

CN804(X-Main) Power D5V VG GND GND VE GND GND VS VS CN805(Y-Main) NO 1 2 3 4 5 6 7 8 9 10 Power D5V VG GND Vscan GND Vset GND GND VS VS CN806/812(Buffer) NO 1 2 3 4 5 Power Va Va N.C. GND GND

[FAN B+:For VMB]

CN807/811(FAN) NO 1 2 5 Power 12V GND Fan_D

2-1. Drive Description on SMPS

Operation Description on SMPS

1. Overview SMPS used in PDP 42" developed into the compact-sized with high efficiency. The asymmetrical half bridge and the flyback converter are applied into all output. To comply with the harmonic restrictions, it takes the power factor improvementcircuit, which converts AC into the high DC

and uses as the input of another converter controller.

2. Input controller SMPS works in whole section of AC 90~264V. It is possible to start in the AC 90 and can restart with new input voltage, even in interruption of electric power. STD_5V comes out when AC is impressed

3. Output Controller Given SMPS have 15 output voltages. The following shows the specification of output voltage and output current in case of their successive drive.

Operation Description on SMPS

Name VS VA VSCAN VSET VE VG D12V Voltage +75V ~ 100V +65V ~ 80V +65V ~ 100V +80V ~ 100V +100V ~ 120V +15V +12V Current(Max.) 4.5A 0.6A 0.1A 0.1A 0.1A 1.5A 0.1A Driving Voltage of Fet Using in PDP Driving Sustain Voltage Address Voltage A6V D5V D3.3V +6V +5V +3.3V 0.1A 1.0A 4.5A 1.7A 0.003A 0.6A Standby for Remote Control Amp Voltage of Audio IC Driving Voltage of Logic Name A12V D6V Voltage +12V +6V Current(Max.) 0.3A 0.1A Using in PDP Driving

12VAMP +12V VT STD_5V +33V +5V

3-1. Overvoltage protection

It has circuit to maintain normal voltage, additionally with circuit for sensing overvoltage, so it means any
overvoltage does not give impacts on other output controller. SMPS prevents overvoltage in the latch mode. VS(85V) works protection function more than 100V, over 94V for VA(75V), over 8.2V for D6V, over 4.7V for D3.3V

Operation Description on SMPS

3-2. Short circuit and overvoltage protection It forms definition that in the short circuit of output controller the output impedance is lower than 300mohm. If the VS output have a short circuit in case of given SMPS, SMPS stops its working. Even in the case of short circuit between main output and STD_5V, SMPS does not break down. When the short circuit is removed, it restarts.

4. Detail Description AC-DC Converter It converts AC into DC by using the power factor improvementcircuit. This converter was designated to

control the high frequency noise, with the function to improve the power factor. This part becomes input
controller of another constant-voltage.

[ PFC Drive FET(SPW47N60) Drain Pulse ]

[ PFC Drive FET(SPW47N60) Gate Pulse ]

Operation Description on SMPS

Auxiliary Power
It is the part to supply power of mycom for remote control. When the power is on, it will work, which means that MICOM is on standby. This output part is stand_by voltage. When the power-on signal from remote control impress, it works main power panel of SMPS via stand_by voltage.

Configuration of VS output Major part of PDF SMPS outputs 85V 5A. It takes asymmetrical half bridge converter and connects 2 converters with 85V output in parallel, which increases efficiency than one 85V converter,

on the other hand, decreases its size.

[ Driving FET(2SK2372) Drain Pulse&Current wave. ]

[ Driving FET(2SK2372) Gate Pulse ]

Operation Description on SMPS

- PWM Part It uses PWM part of ML4824, but there are some points to take cautions. As this part is synchronized with the PFC part, PWM wave in the current mode drive is induced via the current sensor resistance or current transformer, and shows the current flowing in the output controller.

DC-DC Converter : Input of VSCAN, VSET and VE belongs to the VS part

[ VSET Pulse ]

[ VE Pulse ]

[ Vscan Pulse ]

Operation Description on SMPS

Output (VA,Multi Outputs) Pulse

[ Va Main Pulse ]

[ Multi Outputs Main Pulse ]

Trouble shooting on SMPS

Power ON Check cord connection OK NG STB_5V

Check the IC2,D28

OK

PFC

Check the IC1,Q1,Q2

OK NG

OK

PFC

Check the IC35

NG PFC

Check the IC7

Trouble shooting on SMPS

NG

VS

Check the Q6,Q8

OK

Vscan VE,Vset OK

Check the IC16, IC17, IC18

Check the Other board ( Image Board or Driver Board ) or Cable.

2-2. Operation Explanation of Driving Circuit

1. Overview of Driver Circuit
1) Definition of Driver Circuit The driver circuit division drives the panel with the proper wave form (high voltage pulse) to develop image on the outside terminal division (X electrode group, Y electrode group, Address electrode). High voltage switching pulse is made by MOSFET combination.

2) Working Principle of Driver Circuit To develop image on the PDP, the voltage should be impressed into the X, Y and ADDRESS electrodes (which are component of each pictorial element) under the proper conditions. The driver wave form which is currently applied to is ADS (Address & Display Separate: Driving method to work by dividing address and constant-current section ) Based on this method, the discharge to be done in the pictorial element of PDP can be divided into 3 types as follows.

Address Discharge: to form the wall voltage within pictorial element by providing lighting pictorial

element with information(impressing data voltage)

: It is the discharge produced by difference between the positive electric potential of address electrode (normally, Va impressed voltage of 70~75V +Positive Wall charge) and negative electric potential of Y electrode (GND level impression+ Negative Wall charge).

Operation Description on Driving Board

Constant-current Discharge: It is the display section to form discharge voluntarily with the help of wall voltage formed by address discharge. (It makes optical power to create image) : It is the Self Sustaining Discharge made by combining the electric potential of coherent pulse, normally 160-170Volt, which alternates the X electrode with Y electrode in the sustain section, with the wall voltage according to the pictorial element condition changed by if the former discharge exists or not. That is to say, it works according to Memory characteristic (it means that former working condition defines the current condition) as the basic feature of AC PDP.

If the wall voltage formerly exists in the pictorial element(i.e., the pictorial element is on), the discharge makes
forms again because the voltage higher than one of the discharging starting time is impressed by combination of the wall voltage and of the next impressed constant-current. While if the wall voltage does not exist in the pictorial element (i.e., the pictorial element is off), the discharge does not form because the voltage could not reach to the level of the discharging starting time, only with constant-current.

Operation Description on Driving Board

Erasing discharge: To selectively perform the address discharge for respective pixel, pixels of all
panels must be on same conditions (same wall charge state and space charge state). Therefore the erasing discharge zone is important factor to obtain driving margins. There are various methods such as application of log waveform but the wall voltage control method by the Ramp Waveform is now widely applied. : The purpose of intialization (Erasing) discharge is to make wall voltage within the the whole of Pixels. In other words, the erasing discharge must make difference between wall voltages uniform depending on whether or not the sustain discharge exists in the previous state. Namely it must remove the wall voltage formed by the sustain discharge and supply ions or elements by causing discharge for removing the wall voltage. In the other words, To remove the wall voltage, limit the time when polarity of the wall voltage is reversely charged by causing discharge or prevent polarity form being reversely charged by supplying appropriate quantity of ions or elements through forming weak discharge [low voltage of erasing]. There are two types of the weak discharge [low voltage]as known so far. 1) Log Waveform adopted by the F-company 2) Weak erasing discharge by the Ramp Waveform largely adopted by Matsushita

company, etc. Outside applied voltage is adjusted depending on difference of wall voltage within Pixel,
since discharge is formed when the sumof the existing wall voltage remained and the voltage on a rising waveform exceed the driving beginning voltage, by slowly applying the rising slope of the erased waveform for these two methods. In addition, weak discharge is formed since the strength of applied voltage is small.

Operation Description on Driving Board

3) Essential factors for driving board operation - Supplied from power board and the optimum value may somewhat differ from the below cases.

Vs

: 85V

- Sustain - Y Rising Ramp - Ve bias

Vset : 60V ~ 70V Ve : 110V

Vscan : 70V ~ 80V - Scan bias

Vdd : 3.3V Vcc : 15V Logic Signal - Logic signal buffer IC - FET Gate drive IC

: Supplied from logic board

: Gate signal of each FET

Driving Waveform Specification Arrangement

Y rising Ramp Y falling Ramp Y sustain Pulse

Y scan Pulse X sustain Pulse

Address Pulse

A1,2..... X Y1,2....

Address(=Data) Electrode Common & Sustain Electrode Scan & Sustain Electrode

Vs Vset Vscan

85V 95V 85V

Ve Va

110V 79V

Explanation of Function per Pulse

Y Rising Ramp Pulse Outside voltage of about 390V~400V is applied to the Y electrode in the Y Rising Ramp zone, and weak

discharge begins if respective gap voltage equals to the discharge beginning voltage.
Negative Wall charges accumulate on the Y electrode and the Positive Wall charges on the X electrode in the whole while weak discharge is maintained.

Y Falling Ramp Pulse Most of Negative Wall charges accumulated on the Y electrode by the X bias of about 200V are used to remove Positive Wall charges in the Y Falling Ramp zone, and most of Positive charges accumulated on the (0V) Rising Ramp zone toward the address electrode are maintained, having distribution of wall charges beneficial for the subsequent address discharge.

Explanation of Function per Pulse

Y Scan Pulse Y scan pulse is called as injection pulse, and selects the Y electrode one by one (Line-at-a-time). In this case, Vscan is called as Scan bias. For the electrode line with the Vscan voltage applied, voltage of about 70 Volt (Vscan) is applied, and voltage of 0 Volt(GN0) is applied.

However, since Negative Wall charges accumulate on the Y electrode by the application of Ramp pulse
and Positive Wall charges accumulate on the address electrode, voltage of more than the discharge beginning voltage is applied to the cell where address pulse(70V~75V) is allotted and thus address discharge occurs. Address time of the PDP is very long since both scan pulse and data pulse must be applied in line at a time.

1st Sustain Pulse The Sustain Pulse always begins from the Y electrode, it is because Positive Wall charges are formed on the Y electrode if address discharge occurs. The wall charges formed by the address discharge are less than those for the sustain discharge, and thus the strength of the initial discharge is weak. Sustain discharge usually become stable after 5~6 times of discharge depending on structure of electrode and environment. Therefore, the initial long sustain pulse is intended to form the initial discharge stable and form the wall charges much as possible as.

Trouble shooting on Driving Board

1. Y buffer
- To check whether there is failure of the Y Main, firstly check normal operation of the Y buffer. - After separating both the Y Main and the Y buffer connector, - Check forward voltage drop of 0.4V ~ 0.5V by diode check between OUTL and OUTH. - In addition, resistance between both ends is also more than several k.

OUTL

OUTH

OUTL OUTH

OUTL

OUTH

Trouble shooting on Driving Board

2. Y Main - After connecting both the Y Main and the Y buffer, check that output of one of OUT1~8 of the Y buffer is done as follows in application of power
OUT1 OUT2
You must check 1EA of Scan pulse is output

OUT3 OUT4 OUT6 OUT5

Trouble shooting on Driving Board

3. X Main - Check output of the TPOUT on the X board is done as follows in application of power

TPOUT

2-3. Operation Explanation of Logic Board

[Logic Block Diagram]
Image Signal Vs Start Logic Power Signal 3.3V,5V

LA03 IIC (SCL,SDA) Vs start U2004 27MHz LVDS SW2001

Image Signal 8 bit per DATA R.G.B 1 bit per H,V SYNC

CN803 28.636MHz X2002 OSC CY2305 U2003 EPC2 U2011 EPC2 U2007 EPC2 U2006 64M SDRAM U2014

X2000 60MHz 64M CY2305 U2002 SDRAM U2013 RESET SPS10-MEM ASIC MEMORY CONTROLLER U2000 Circuit X CONTROL X CONTROL CN101

EP20K400EBC652-1 Y CONTROL Y CONTROL CN201 28BV256K U2001 IIC VCC(3.3V) GND IIC(SCL,SDA) CN2002 CN401
ADRV101~106 ADRV201~206 ADRV301~306 CLK,BLK,POL,STB

FPGA FRONT_XY U2005

8 bit per DATA R.G.B 1 bit per H,V SYNC 1 bit per DATA_EN,TSC,POL,SEN,SDA,SCLK _nRESET

40MHz X2001

CLK_XY(20MHz),SV_SYNC nRESET

ADRV401~406 CLK,BLK,POL,STB

CN402

ADRV501~506 ADRV601~606 ADRV701~706 CLK,BLK,POL,STB

CN403

e-buffer

f-buffer

g-buffer

Definition of Name and Terms on Logic Board

M O D E L

LOGIC BOARD OPTION S/W STATUS

ON

REMARKS
External : 2,4 On : 3 On

42" SD
1 2 3 4

OFF Internal

No. Item LVDS connector LED for operation check I2C connector 256K Y connector X connector CN401(E-address buffer connector) CN402(F-address buffer connector) CN403(G-address buffer] connector) Power connector Power fuse OPTION S/W

Explanation Connector for receiving RGB, H, V, DATAEN, DCLK encoded in the LVDS from image board. LED to show that Sync, clock is normally input into the logic board Connector connecting the Key Scan Board that checks and adjusts 256K data Eeprom to save table, APC table, driving waveform timing and other option, etc Connector to output control signal of the Y driving board Connector to output control signal of the X driving board Connector to output address data, control signal to the E-buffer board Cnnector to output address data, control signal to the F-buffer board Connector to output address data, control signal to the G-buffer board Connector to receive power 95V] to the logic board Fuse attached to power [5V] to the logic board Inner/Outer cut-off S/W

Explanation of Logic Board

Logic board is composed of a logic main board that generates and outputs the address driver output signal and the XY driving signal by processing image signal, and a buffer board that buffers the address driver output signal and delivers it to the address driver IC (COF Module).

Logic Board

Function
- Processes Image signal (W/L, error dispersion, APC) - Outputs image signal as address driver control signal, data signal buffer board - Outputs the XY driving board control signal

Remarks

Logic Main

E Buffer board

- Delivers data signal and control signal to the right/right COF - Delivers data signal and control signal to the middle/lower COF - Delivers data signal and control signal to the Right/ Lower COF

Buffer Board

F Buffer boadr

G Buffer board

2-4. Explanation of Scaler(Image Board) Operation

DIGITAL BOARD IC & SIGNAL BLOCK DIAGRAM
CRYSTAL TO LOGIC DS90C385 Z86129 M 2 7 V 1 6 0 ANALOG Signal DIGITAL Signal FROM SMPS CLOCK Signal

K4S643232E SNI K4S643232E FLI2200

VPC3230

CVBS

20.25M K4S641632E K4S643232E ASI500 K4S643232E SDA6000 BA7657 VPC3230 20.25M 14.3181M K4S643232E M27V160

Y/C

Y/Pb/Pr/H/V

AD9883 FROM CONTROL PCB 6M SiI161A

74HC4052

DVI L/R R/G/B/H/V D-SUB L/R

S-VHS Y/C

DVI,D-SUB L/R S-VHS L/R

RS-232

DVI

DVI SOUND

D-SUB

D-SUB Sound

S-VIDEO

S-VIDEO/VIDEO Sound

Explanation of Scaler(Image Board) Operation

ANALOG BOARD IC & SIGNAL BLOCK DIAGRAM
CN801
FROM SMPS CRYSTAL ANALOG SIGNAL DIGITAL SIGNAL CLOCK SIGNAL

18.432M

Y/C CN101

UPD64083

20M

SUB WOOPER CVBS CVBS DVI,D-SUB L/R Y/Pb/Pr/H/V S-VHS L/R

CXA2151 4M MSP3451

L/R CN102

S-CVBS
TEA6425

Y/Pb/Pr
BA7657 TA1101

M-CVBS
TUNER 2 TUNER 1

CN103 VIDEO-CVBS Y/Pb/Pr 1 Y/Pb/Pr 2

VODEO

COMPONENT1

COMPONENT1 SOUND

COMPONENT2

COMPONENT2 SOUND

SOUND OUTPUT

RF INPUT

Sub-woofer Output

Factory Data per each Mode

1. UPD 64083 (COMB FILTER)
ITEM VAPGAIN VAPINV YPFP YPFG TV/Video/S-Video/Component 1,2(SD) 4 16 3 9 Component 1,2(HD) 4 16 3 9 PC 4 16 3 9 DVI 4 16 3 9

2. VPC 3230(M) : Main VCD

ITEM CONTRAST BRIGHTNESS PEAKING CORING LUMA DELAY HPLL SPEED YUV CONTRAST YUV BRIGHTNESS YUV SATCB YUV SATCR YUV TINT SATURATION TINT TV/Video/S-Video/Component 1,2(SD) 43 47 5 0 255 1 29 68 42 42 3 2000 32 Component 1,2(HD) 43 47 5 0 255 1 29 68 42 42 3 2000 32 PC 43 47 5 0 255 1 29 68 42 42 3 2000 32 DVI 43 47 5 0 255 1 29 68 42 42 3 2000 32

Factory Data per each Mode

3. VPC 3230(S) : SUB VCD
ITEM PIP CONTRAST PIP BRIGHTNESS YUV CONTRAST YUV BRIGHTNESS LUMA DELAY H POSITION V POSITION TV/Video/S-Video/Component 1,2(SD) 43 47 29 68 255 0 0 Component 1,2(HD) 43 47 29 68 255 0 0 PC 43 47 29 68 255 0 0 DVI 43 47 29 68 255 0 0

4. FLI 2200 (De-Interlacer)

ITEM Y CLAMP C CLAMP Y DELAY C DELAY MOTION DETECT TV/Video/S-Video/Component 1,2(SD) 64 512 4 11 48 Component 1,2(HD) 64 512 4 11 48 PC 64 512 4 11 48 DVI 64 512 4 11 48

Factory Data per each Mode

5. ASI500 (SCALER MAIN / OSD)
ITEM
R CONTRAST G CONTRAST B CONTRAST R BRIGHTNESS G BRIGHTNESS B BRIGHTNESS TEXT ALPHA TEXT THRESHOLD FILTER ML FILTER MR FILTER FR FILTER MC FILTER UC FILTER LC FILTER YPASS R GAMMA G GAMMA B GAMMA H POSITION V POSITION H SIZE V SIZE OVERSCAN B OVERSCAN G OVERSCAN R

TV/Video/S-Video/Component 1,2(SD)

Component 1,2(HD)
32 32 32 0 0 0 1 7 0 0 0 16 0 0 0 32 32 32 0 0 0 0 63 63 63

PC

DVI

Factory Data per each Mode

6. ASI500 (SCALER PIP)
ITEM PIP R CONT PIP G CONT PIP B CONT PIP R BRIGHT PIP G BRIGHT PIP B BRIGHT PIP FILTER LC PIP FILTER ML PIP FILTER MR PIP FILTER UC TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) 32 32 32 0 0 0 0 0 0 0 PC DVI

8. CXA2151HD (COMPONENT MUX)

ITEM GAIN-SEL CR GAIN CB GAIN Y GAIN TV/Video/S-Video/Component 1,2(SD) 1 7 7 7 Component 1,2(HD) 1 7 7 7 PC 1 7 7 7 DVI 1 7 7 7

Factory Data per each Mode

7. DNIe (Picture Enhancer)
ITEM BRIGHT OFFSET CONTRA OFFSET NR SCALE MAX NR SCALE MIN DE GAIN COR DE GAIN CLIP CE UPPER CE CUTOFF CE GAIN WTE Y THRE R CTL SYNC MODE PATT SEL RED CONPENSA BLUE CONPENSA WTE GAIN RAST VSIZE RAST HSIZE SHARP OFFSET TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) 0 0 52 18 3 60 240 64 48 230 2 1 0 616 616 58 1023 895 0 PC DVI

Factory Data per each Mode

9. AD 9883 (AD Converter)
ITEM R GAIN G GAIN B GAIN R, CR OFFSET G, Y OFFSET B, CB OFFSET Auto Color TV/Video/S-Video/Component 1,2(SD) 142 142 142 60 48 64 Component 1,2(HD) 142 142 142 60 48 64 PC 142 142 142 54 54 54 DVI 142 142 142 60 48 64

10. Logic (PDP Driver)

ITEM R DRIVE G DRIVE B DRIVE R CUTOFF G CUTOFF B CUTOFF GAMMA GTS SET ERD MODE RANDOM NOISE DIFF FILTER APC APC SET APC VALUE ACTIVE VPOS ACTIVE HPOS VSYNC POS HSYNC POS VSYNC WIDTH HSYNC WIDTH TV/Video/S-Video/Component 1,2(SD) 140 130 120 0 0 0 Component 1,2(HD) 140 130 120 0 0 0 1 0 2 0 1 1 0 127 12 19 3 32 2 12 PC 140 130 120 0 0 0 DVI 140 130 120 0 0 0

Factory Data per each Mode

11. TP LOG-ASI : Test Pattern LOGIC/SCALER
ITEM LOG PATTERN LOG HIGH LEVEL LOG LOW LEVEL ASI COLORBAR TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) 0 255 0 0 PC DVI

12. Option
ITEM PIX SHIFT SHIFT TEST PIX NUMBER SHIFT LINE SHIFT TIME COUNTRY TEMP PROTECT SNI DEMO SNI THROUGH VIDEO MUTE IRC AFN LANGUAGE CUSTOMER TUNER TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) 0 0 2 1 4 0 0 0 0 10 0 0 0 0
0 : OFF 1: ON 1 : THROUGH 0 : NOT THROUGH Unit : 100msec 0 : for customer 0 : English 0 : CE 0:1 TUNER 1 : for military 2 : Spanish

PC

DVI
0 : OFF 0 : minute

Remark
1 : ON 1 : second

Number of shifted Lines horizontally Number of shifted Lines vertically Time fixed at SHIFT TEST 0 : domestic 1 : USA 2 : Japan

1 : French 1 : VMB 1:2 TUNER

Signal Waveform at AV(Audio & Visual) Board

Input Signal : 8-Color Bar

ANALOG BOARD IC103(TEA6425D) PIN6(VIDEO-CVBS)

ANALOG BOARD CN102 PIN12(3D_Y_OUT)

ANALOG BOARD CN102 PIN10(3D_C_OUT)

DIGITAL BOARD IC101(VPC3230D-C5) PIN57(VPC_VSYNC)

Signal Waveform at AV(Audio & Visual) Board

Input Signal : 8-Color Bar

DIGITAL BOARD IC101(VPC3230D-C5) PIN56(VPC_HSYNC)

DIGITAL BOARD IC101(VPC3230D-C5) PIN28(VPC_CLK)

DIGITAL BOARD IC104(FLI2200) PIN91(FLI_VSYNC)

DIGITAL BOARD IC104(FLI2200) PIN92(FLI_HSYNC)

* Dimensions in mm

Signal Waveform at AV(Audio & Visual) Board

Input Signal : 8-Color Bar

DIGITAL BOARD IC104(FLI2200) PIN90(FLI_DE)

DIGITAL BOARD IC104(FLI2200) PIN117(FLI_CLK)

DIGITAL BOARD RW507(ASI500 OUTPUT) PIN2(MN_IN_V)

DIGITAL BOARD RW507(ASI500 OUTPUT) PIN1(MN_IN_H)

Signal Waveform at AV(Audio & Visual) Board

Input Signal : 8-Color Bar

DIGITAL BOARD RW507(ASI500 OUTPUT) PIN4(MN_IN_CLK)

DIGITAL BOARD IC601(SNI OUTPUT) PIN9(OUT_VSYNC)

DIGITAL BOARD IC601(SNI OUTPUT) PIN10(OUT_HSYNC)

DIGITAL BOARD IC601(SNI OUTPUT) PIN8(OUT_DE)

Signal Waveform at AV(Audio & Visual) Board

Input Signal : 8-Color Bar

DIGITAL BOARD IC601(SNI OUTPUT) PIN12(OUT_CLK)

ANALOG BOARD IC101(CXA2151 OUTPUT) PIN27(COMP_Y)

ANALOG BOARD IC101(CXA2151 OUTPUT) PIN26(COMP_PB)

ANALOG BOARD IC101(CXA2151 OUTPUT) PIN25(COMP_PR)

Signal Waveform at AV(Audio & Visual) Board

Input Signal : 8-Color Bar

ANALOG BOARD IC101(CXA2151 OUTPUT) PIN23(COMP_V)

ANALOG BOARD IC101(CXA2151 OUTPUT) PIN22(COMP_H)

DIGITAL BOARD IC705(AD9883 OUTPUT) PIN64(ASI_SUB_V)

DIGITAL BOARD IC705(AD9883 OUTPUT) PIN66(ASI_SUB_H)

Signal Waveform at AV(Audio & Visual) Board

Input Signal : 8-Color Bar

DIGITAL BOARD IC705(AD9883 OUTPUT) PIN65(ASI_SUB_SOG)

DIGITAL BOARD IC705(AD9883 OUTPUT) PIN67(ASI_SUB_CLK)

DIGITAL BOARD IC702(SII169CT OUTPUT) PIN47(DVI_VSYNC)

DIGITAL BOARD IC702(SII169CT OUTPUT) PIN48(DVI_HSYNC)

Signal Waveform at AV(Audio & Visual) Board

Input Signal : 8-Color Bar

DIGITAL BOARD IC702(SII169CT OUTPUT) PIN46(DVI_DE)

DIGITAL BOARD IC702(SII169CT OUTPUT) PIN44(DVI_CLK)

Trouble Shooting for PDP Set

Turn on the set Protection or LED Normal NO LED problems Remove all Connectors from SMPS(except AV) and Check the protection or voltages NO Change SMPS NO Change X-Main NO OK Connect X-Main OK Connect Y-Main OK Connect Address Buffer Change Y-Main OK NO LED Remove NO Check PS_ON(0V : SMPS CN802 pin4) & Check stand_by 5V(SMPS CN802 pin2) OK Check the Key-Pad Remove all Connectors NO from SMPS and Check the voltages on AV Boards NO Only Vs or Va cannot be measured Check VS_ON(3V) CN803(SMPS pin2) NO Change Logic Change SMPS OK Change Digital NO OK Check other Boards

Change Address Buffer

Check Voltages on the SMPS (Vs,Va,Ve,Vset..) OK Check the damaged components on X,Y-Main & Address Board Yes

Connectors from

NO

Almost No Voltages on the SMPS?

X,Y-Main,Address Buffers and Check the voltages on SMPS again OK

NO Voltages Change SMPS

Change the damaged Board

NO Damaged Components Check the Fuses on X,Y-Main Boards (F4003,F5003) OK Change Y-Main NO Change X-Main NO NO Change the damaged Board

I can see some Video ex) TV,Video or etc Inputsource Check whether always No Video about all AV inputs

Change Analog Change Check the NO LVDS cable NO Change Logic

NO, can't see any Video

Digital

Comparison with New Models

Project
Design

Alexander (V2)

Mozart (V3)

Nelson (V3)

Brightness Contrast ratio

700cd/m2 1200:1

1000cd/m2 3000:1

1000cd/m2 3000:1

Tuner
Audio out Sound Speaker Video input S-Video input Component Input Side Input DVI Power Consumption Etc.

2Tuner
10W x 2 Dolby Virtual Not Included 1Rear 1Rear 2Rear 1Rear 330W -

2Tuner
15W x 2 SRS Tru Surround XT Included 2Rear 1Rear 2Rear CVBS, S-Video 1Rear 330W Touch Pad, Melody

1Tuner
15W x 2 SRS Tru Surround XT Not Included 1Rear 1Rear 1Rear 1Rear 330W -