Layout & Design Rules

Introduction
Physical mask layout of any circuit to be manufactured using a particular process must follow a set of rules. They usually specify min allowable line widths for physical object on chip. Main objective of design rule is to achieve a high overall yield and reliability using smallest possible Silicon area.

Micron & Lambda Rules

The design rules are usually described in two ways: i) Micron Rule: Min feature size and allowable feature specification are stated in terms of absolute dimension in micron . ii) Lambda Rule: Specify layout constrains in terms of a single parameter and thus allow linear proportional scaling of all geometrical constrains. N.B: DRC(Design rule checker )is used to check design, whether it satisfy design rule or not

Basics of Lambda Rules

Stick Diagram
Stick diagrams are a design technique that represent the layout for a device They are used as an intermediary step between schematic and layout Here, the detailed layout design rules are simply neglected and the main features (active areas, polysilicon lines, metal lines) are represented by constant width rectangles or simple sticks They can save a lot of time in transistor placement and device minimization
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Coloured Stick Diagram Notation

Silicon layers are typically colour coded as follows :
diffusion (device well, local interconnect) polysilicon (gate electrode, interconnect) metal (contact, interconnect) contact windows N well (CMOS devices)

This colour representation is used during mask layer definition Translation from circuit format to a mask layout (and vice-versa) is relatively straightforward
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Stick Diagrams

N+

N+

Stick Diagrams
VDD VDD

X
X X

Stick Diagram

X Gnd

Gnd

Stick Diagrams
VDD X X X VDD

X Gnd

Gnd

From schematic to stick diagram

Some important points while drawing stick diagrams : - Use minimum Active. - Fully use as much contact area as you have - Try to use shared Active regions. An example: Three transistors in series do not need the Metal1 and contacts between each of the gates and can all be on one piece of active as shown in the stick diagrams. - Where possible avoid crossing nets.
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Stick Diagrams-Basic Gates

Fig a. Inverter Fig b. 3-input NAND gate

Layout of Complex CMOS Logic Gates

Construct a logic graph from schematic Identify each transistor with a unique name

Layout of Complex CMOS Logic Gates

Construct one Euler path for both PUN & PDN Euler paths are defined by a path where each edge visited by only once. Find a common Euler path for PUN & PDN. Rearrange inputs according to Euler path & draw stick diagram

Layout of Complex CMOS Logic Gates

Q= (ab+cd) One common Euler path is : c-a-b-d

Schematic from layout

Logic function is: x=(c(a+b))

Home work
Draw stick diagram & simplified layout of following: i) y= (a+b+c) ii) Y=((a+b.(c+d).e) iii) Y=(ab(c+d)) iv) Y=(a(d+e)+bc)

THANK YOU