TOPIC 4 :

MEMORY SYSTEM

At the end of the class you should :

Understand memory in computer systems
State functions of main memory. Identify types of ROM: ROM, PROM, EPROM, EEPROM and Flash ROM. State the difference between SRAM and DRAM. Determine memory size of standard memory chips. Explain memory chip control signals.

Main Memory
Functions : Is a memory that hold the instruction and data while program is running for storing data so the CPU/MPU and other direct memory access devices can call up to fetch or store data for processing. It is very much like some part of our brain, that stores short term and long term memory.

RAM vs ROM
RAM Random Access Memory ROM Read Only Memory

It is a volatile type of memory that needs electricity to flow to retain information

RAM offers a very fast memory access

Non-volatile type of memory essentially it is a piece of permanently written information stored as memory
ROM is generally slower memory access than RAM

RAM vs ROM
RAM ROM

Data can be written to or read from

Data stored in RAM is lost when power is removed This means data stored in RAM should be stored in a more permanent location, like a floppy disk or hard drive, before system power is removed Because of RAMs inability to store data when power is removed, it is considered to be volatile memory

Data can be read only

Data in the memory chip remains stored even when power is taken away from the chip

Because of ROMs ability to store data even when power is removed, it is considered to be non-volatile memory

ROM
Firmware (Program instruction used frequently)

Program stored in a ROM

graphics cards, disk controllers.

Types of ROM
Read Only Memory (ROM)
Actual ROM chips are programmed when they are made and can never be changed. Program stored in a ROM
Boot time code, BIOS (basic input/output system) graphics cards, disk controllers.

Programmable ROM (PROM)

Suitable for development work since they can be programmed by the developer. The developer can burn information into the PROM. PROMS consists of arrays of semiconductor capacitors. Different capacitors can be addressed by applying a pattern of signals to the address pins of the PROM chip. A charged capacitor represents a binary zero while a discharged capacitor represents a binary 1. The capacitors are isolated from one another so there is very leakage. However, over many years or at very high temperatures, the charge stored in the capacitor may be lost. On occasion it is desirable to erase all the information from a PROM and reprogram it with new data

Types of ROM
Erasable programmable ROM (EPROM) Have a transparent window that allows ultraviolet light to penetrate the semiconductor material inside The ultraviolet light gives electrons additional energy allowing them to tunnel through the insulating layers. Thus, the capacitors are discharged. Each cell within the memory chip now represents a binary 1 and the chip can be reprogrammed

Electrically Erasable PROM (EEPROM) Dont need ultraviolet light to erase the contents, only electrical signals

Types of ROM
Electrically Erasable PROM (EAPROM) EEPROM is also known as EAPROM the EA being an abbreviation for Electrically Alterable. The major benefit to EE or EAPROM is that the chips do not have to be removed from the circuit to change their program.

Flash ROM
Also called flash memory A special type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time

SRAM vs DRAM
Static RAM Dynamic RAM

DRAM stores 1s and 0s as charge on a small MOS capacitor

High capacity Low power requirement Moderate operating speed Data has to leak off after a period of time, DRAM requires periodic recharging or the memory cells; this is called refreshing DRAM

SRAM vs DRAM
Static RAM Dynamic RAM

Static RAM is random access memory that retains data bits in its memory as long as power is being supplied
SRAM does not have to be periodically refreshed. Static RAM does not need refreshing because it operates on the principle of moving current that is switched in one of two directions rather than a storage cell that holds a charge in place Static RAM provides faster access to data and is more expensive than DRAM DRAM is dynamic in that, it needs to have its storage cells refreshed or given a new electronic charge every few milliseconds. DRAM stores each bit in a storage cell consisting of a capacitor and a transistor. Capacitors tend to lose their charge rather quickly; thus, the need for recharging

SRAM vs DRAM
Static RAM Dynamic RAM

SRAM is used for a computers cache memory and as part of the random access memory digital-to-analog converter on a video card

Dynamic random access memory (DRAM is the most common kind of random access memory RAM) for personal computers and workstations

SRAM vs DRAM
Static RAM Dynamic RAM

SRAM use digital flip-flops to store the required binary information

DRAM use MOS capacitors. Because of the capacitive nature of the storage element, dynamic RAMs require less space per chip, per bit, and thus have larger densities DRAM employ MOS capacitors that retain their charges (stored information) for short periods of time

SRAM draw more power per bit Because SRAM must saturate transistors within the flip-flop to retain the stored binary information, and saturated transistors dissipate maximum power

SRAM vs DRAM
Static RAM Dynamic RAM

Disadvantages : 1. From the usage of MOS capacitor as the storage element. Left alone, the capacitor will eventually discharge, thus losing the stored binary information. For this reason the DRAM must constantly refreshed to avoid data loss. During a refresh operation, all of the capacitors within the dynamic DRAM are recharged 2. The refresh operation takes time to complete, and the DRAM is unavailable for use by the processor during this time

SRAM vs DRAM
Static RAM Dynamic RAM

SRAM require no refresh, they are available to the CPU 100 percent of the time

Disadvantages : Older DRAMs required that all storage elements inside the chip ware refreshed every 2 ms. Newer DRAMs have an extended 4ms refresh time, but the overall refresh operation ties up an average of 3 percent of the total available DRAM time, which implies that the CPU only has access to the DRAM 97 percent of the time

SRAM vs DRAM
Static RAM Dynamic RAM

Bits stored as on/off switches

No charges to leak No refreshing needed when powered More complex construction

Bits stored as charge in capacitors

Charges leak Need refreshing even when powered Simpler construction

Larger per bit More expensive

Does not need refresh circuits Faster Cache

Smaller per bit Less expensive

Need refresh circuits Slower Main memory

Digital -Uses flip-flops

Essentially analogue -Level of charge determines value

SRAM vs DRAM
SRAM does not need to be refreshed Faster transistors inside would continue to hold the data as long as the power supply is not cut off SRAM modules are also much simpler needs a lot more transistors for every bit of data - 6 Expensive DRAM requires the data to be refreshed periodically in order to retain the data slower and less desirable The additional circuitry and timing needed to introduce the refresh DRAM modules are complicated needs a transistor and a capacitor for every bit of data lower price

Commonly used in cache memory speed used in main memory is crucial

Low power consumption High power consumption

Summary sram vs dram

SRAM are fast, require no refresh and have low bit densities DRAM are slower and require extra logic for refresh and other timing controls, but are cheaper, consume less power, and have very large bit densities

memory size of standard memory chips Pin Connection Of RAM

memory chip is normally recognized by its memory capacity. Which has 2 main elements : i) Address Size ii) Data Size 32 x 4 4K x 8 2K x 8 (Address Size) (Data Size) memory chip has many pins with specific function of each pin or group of pins : i) Address ii) Data iii) Chip Capacity * 1 Kbyte = 1024 Bits iv) The Control lines/pins - Control R/W - Memory Enable (ME) v) Pins Layout of memory chip

ex : chip capacity label 32 X 4

i) Address How to determine address lines or pins?

has address size of 32 memory location / cells

(where each cell has a data size of 4 bits) 2n = 32 log 2n = log 32 n log 2 = log 32 n = log 32 / log 2 =5 5 address lines / pins which labeled as An = A1, A2, A3, A4

ex : chip capacity label 32 X 4

ii) Data How to determine data lines or pins?

has data size of 4 bits

4

data lines / pins which labeled as Dn = D0, D1, D2, D3

ex : chip capacity label 32 X 4

iii) Chip Capacity
Chip Capacity label 32 X 4 = 128 bits

iv) The Control lines / pins

Control R / W R = logic 0 to run READ operation W = logic 1 to run WRITE operation Memory Enable (ME) memory is made up of several memory chips connected together. each chip represents certain range of address, thus we need to set the only appropriate chip to be made active whereas the others set inactive. this is done by sending a logic to the control pin ME. ME = logic 0 = memory Disable ME = logic 1 = memory Enable

ex : chip capacity label 32 X 4

v) Pins Layout of memory chip

Exercise :
A memory chip with capacity of 5K x 8, determine :

a) numbers of data lines b)numbers of address lines c) capacity in Bits, Byte, Kbyte d) draw the pins layout block diagram

At the end of the class you should :

Understand memory systems design
Explain the operation of bus buffering

The 68000 Address and Data Buses

16-bit data bus capable of reading and writing 8 and 16 bits information 24-bit address bus can address up to 16MB of external memory A1 through A23 are available for use A0 is used inside to control UDS and LDS

Bus Buffering
Standard buses control bus, data bus, and address bus Why buffer needed? So that many gates can be connected to them instead of the few that can be directly driven by the unbuffered address or data line

Bus Buffering
The output of logic circuits has limited capability of how many next stage circuits it can drive, a.k.a., fanout of the circuit
If the output is overloaded with more circuits than the designed fanout, the circuit may not function properly due to slowing down

Similarly, the pins of 68000 control/data/address buses

Can only drive a limited number of devices However, they may need to connect to multiple memory modules and I/O devices

Bus Buffering
Buffer the bus signals of CPU using high-current buffer before connecting to external memories E.g., the address bus line of 68000 can only drive 3.2mA current, the output line of a high-current buffer, 74LS244 can drive 24mA current

Extra notes : (terminologies)

The term Fan Out is a measure of how many loads a pin can drive. This is usually normalized to the load of a standard TTL input, which is considered to be a Fan In of 1. This is a digital logic term, not necessarily just a microprocessor term. Fan In and Fan Out are important, because you do not want to exceed the rated load placed on a pin without providing extra buffering.

Operation of bus buffering

Address Bus Buffering

Data Bus (Bidirectional) Buffering

At the end of the class you should :

Understand memory systems design
Explain method for storing and reading data from memory system

Storing and Reading data from memory system

A general procedure of memory access (read)
1. CPU pulls up R/!W signal to indicate a Read operation 2. CPU puts memory address on the address bus 3. CPU asserts !AS, !UDS/!LDS to indicate valid address, and waits 4. Once memory sees active !AS, it assumes valid address on address bus, reads out data from memory module and puts it on data bus, then assert !DTACK 5. CPU waits till it sees active !DTACK, then read data from the data bus

READ

READ

READ

READ

READ

READ

READ

READ

WRITE

At the end of the class you should :

Understand memory systems design
Design memory address decoder by using full and partial address decoding Develop the memory mapping for a microprocessor-based system. Draw the memory system diagram for microprocessor-based systems. Design the memory system to facilitate memory expansion.

Memory Address Decoding

The need for memory address decoding arises from the fact that the main memory of a computer system is not constructed from a single component, which uniquely addresses each possible memory location. Imagine a situation where two 1M memory chips are connected to a 32-bit address bus to make 2M of memory available. Each memory chip will need twenty address lines to uniquely identify each location in it. If the address lines of each memory chip were simply connected to the first twenty CPU address lines, then both memory chips would be accessed simultaneously whenever the CPU referred to any address. There are several memory addressing schemes that address this problem.

Full Address Decoding

Full address decoding is when each addressable location within a memory component corresponds to a single address on the CPU's address bus. That is, every address line is used to specify each physical memory location, through a combination of specifying a device and a location within it. Full address decoding is very efficient in the use of the available address space, but is often impracticable to use because of the excessive hardware needed to implement it. This is particularly true where devices with a small number of addressable locations (for example memorymapped I/O devices) are used.

Partial Address Decoding

This is the simplest and least expensive form of address decoding. We could connect the chip select input of one memory chip to the last CPU address line, and the chip select input of the other to the same address line but via an inverter. In this way the two chips would never be accessed simultaneously. However, this is very inefficient. Eleven of the address lines are not used, and one of the two memory chips is always selected. The usable address space of the computer has been reduced from 4G to 2K. Partial address decoding is used in small dedicated systems where low cost is the most important factor. The penalty paid is that not all the address space can be used, and future expansion will be difficult.

Difference between :Full Address Decoding

All the address lines are used to specify a memory location Each physical memory location is identified by a unique address

Partial Address Decoding

Since not all the address space is implemented, only a subset of the address lines are needed to point to the physical memory locations Each physical memory location is identified by several possible addresses (using all combinations of the address lines that were not used)

Full Address Decoding

Full address decoding is when each addressable location within a memory component corresponds to a single address on the CPU's address bus. That is, every address line is used to specify each physical memory location, through a combination of specifying a device and a location within it. Full address decoding is very efficient in the use of the available address space, but is often impracticable to use because of the excessive hardware needed to implement it. This is particularly true where devices with a small number of addressable locations (for example memory-mapped I/O devices) are used.

Full Address Decoder Design

1. 2. 3. 4. 5. 6. 7. Determine available information. Determine the required number of address lines. Set base address. Determine lower address range. Determine upper address range. Design decoder. Draw memory block diagram

Example

512kWords (1024 kB) of RAM needs to be interfaced to a 68k-based system, The base address is $400000. Design the decoder circuit.

Step 1: Determine Available Information

Three things must be determined:
How much memory to interface. Base address of memory. How many chips need to be used.

1024 kB (512 kWords)

Chip #1 (512 kB) (even addresses)

Chip #2 (512 kB) (odd addresses)

* Controlled by UDS

* Controlled by LDS

Step 2: Determine Number of Required Address Lines

Determines how many address lines need to be used by one chip. Use the following formula:

log 10 y x log 10 2

y = storage size of one chip (kB) x = number of reserved lines

 Each chip contains 512,000 memory locations:

Needs 19 address lines.

2 x 512 ,000
x log10 2 log10 512 ,000
log10 512 ,000 5.7093 x 18 .97 19 log 10 2 0.3010 *Always round to higher.

Step 3: Allocate Address Line

Address lines allocated based on Step 2. Start with A1. Fill with dont cares (X).

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

X X X X X X X X X X X X X X X X X X X

19 lines allocated UDS/LDS (reserved)

Step 4: Set Base Address

Set base address using the remaining address lines.
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

4 UDS/LDS (reserved) * Base address is $400000

Step 5: Determine Lower Address Range

Replace all dont cares and A0 with zeros. Should get the same base address as question.
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 4

Fill with zeros

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1
4

0
0

0
0

0
0

0
0

0
0

Lower range: $400000

 Replace all dont cares and A0 with ones. This determines the upper limit of the memory chip address.
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Step 6: Determine Upper Address Range

1 4

Fill with ones

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 4

1 F

1 F

1 F

1 F

1 F

Upper range: $4FFFFF

Step 7: Design Decoder using Remaining Addresses

The decoder must be designed so that only the specific bit combinations in the base address can generate a zero on CS (output). Typically uses NAND gate. AS must be included together in decoder.

A23
A23 A22 A21 A20

A22

1 4

A21
A20 AS

NAND

CS

 Actual Implementation
EVEN ODD

A1 A19

D8 D15

A1 A19

CS E

WE

WE CS

MAD
A23 A22 A21 A20 AS
NAND

UDS CS

R/W

LDS

D0 D7

512kB RAM

512kB RAM

Step 8: Draw Memory Block Diagram

Memory block diagram shows assignment of memory addresses. Begins at $000000, ends at $FFFFFF. Mark the locations where memory has been interfaced.
$000000 unused

Interfaced with M68k (1024 kB RAM)

$400000 $4FFFFF

(Lower Range) (Upper Range)

unused $FFFFFF

Partial Address Decoding

This is the simplest and least expensive form of address decoding. We could connect the chip select input of one memory chip to the last CPU address line, and the chip select input of the other to the same address line but via an inverter. In this way the two chips would never be accessed simultaneously. However, this is very inefficient. Eleven of the address lines are not used, and one of the two memory chips is always selected. The usable address space of the computer has been reduced from 4G to 2K. Partial address decoding is used in small dedicated systems where low cost is the most important factor. The penalty paid is that not all the address space can be used, and future expansion will be difficult.

Partial Address Decoding Example

D8 D15
CS A12 OE CS OE D0 D7 D0 D7 A1 A11 A1 A11

2kB ROM

2kB ROM

SELROM UDS LDS

AS

MAD
UDS SELRAM CS A1 A11 E D8 D15 A1 A11 CS E LDS

*Not all address lines used: A12 for MAD A1 A11 for addressing

2kB RAM

2kB RAM

Comparison between FAD and PAD

Full Address Decoder Uses all lines for addressing or decoding. Partial Address Decoder Uses only a part of address lines for addressing or decoding. The rest is ignored. Less complex circuit, since only a few address lines are used. When M68k system has small memory requirements.

Address lines used

MAD circuit

More complex circuit, since need to use all address lines. When the M68k system is large and requires a lot of memory. Easy to upgrade, extra memory can be added with little modifications to original decoder.

When to use

Upgrade

Difficult to upgrade, requires complete redesign of decoder.

Comparison between FAD and PAD cont

Full Address Decoding
All the address lines are used to specify a memory location

Partial Address Decoding

Since not all the address space is implemented, only a subset of the address lines are needed to point to the physical memory locations Each physical memory location is identified by several possible addresses (using all combinations of the address lines that were not used)

Each physical memory location is identified by a unique address

Full Address Decoder

Full Address Decoder cont

Full Address Decoder cont

Full Address Decoder cont

Full Address Decoder cont

Full Address Decoder cont

Full Address Decoder cont

Full Address Decoder cont

Partial Address Decoder

Partial Address Decoder cont

Partial Address Decoder

Partial Address Decoder

Partial Address Decoder

DESIGN MEMORY ADDRESS DECODER

Memory Chip PROM-0 PROM-1 PROM-2 PROM-3 Capacity of chip 2K x 8 2K x 8 2K x 8 2K x 8

Step 1 : Identify how many chips we need to address and the capacity of each chip. For instance .....

DESIGN MEMORY ADDRESS DECODER CONT

Memory Chip PROM-0 Range Start 0000 Range End 07FF

PROM-1
PROM-2 PROM-3

0800
1000 1800

0FFF
17FF 1FFF

Step 2 : Determine the chip Address Range. As shown in the memory mapping section, for the fixed data size of 8 bits, each chip (same capacity) has the same location size of : 2K = = = 2 x 1024 204810 80016

DESIGN MEMORY ADDRESS DECODER CONT

Step 3 : Determine Address lines. Memory Block = 0000 until 1FFF = 200016 = 819210 2n = 8192 log 2n = log 8192 n log 2 = log 8192 n = log 8192 / log 2 = 13 An = A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12

DESIGN MEMORY ADDRESS DECODER CONT

PROM-0 PROM-1

PROM-2
PROM-3

0000 07FF 0800 0FFF 1000 17FF 1800 1FFF

A12 0 0 0 0 1 1 1 1

A11 0 0 1 1 0 0 1 1

A10 0 1 0 1 0 1 0 1

A9 0 1 0 1 0 1 0 1

A8 0 1 0 1 0 1 0 1

A7 0 1 0 1 0 1 0 1

A6 0 1 0 1 0 1 0 1

A5 0 1 0 1 0 1 0 1

A4 0 1 0 1 0 1 0 1

A3 0 1 0 1 0 1 0 1

A2 0 1 0 1 0 1 0 1

A1 0 1 0 1 0 1 0 1

A0 0 1 0 1 0 1 0 1

Step 4 : Draw out the Address Line Tables :

Step 4 cont :

DESIGN MEMORY ADDRESS DECODER CONT

From the above table : (a) Since all chip has similar START / END address bits for address lines : A10 A0; Thus A10 A0 are the common lines to all chips. (b) Address line that changes : A12 A11 To simplify the above table, We group the common lines in hex digit instead of bits. Two LSD are common, Whereas the two MSD will distracted into bits. The simplified table will be as follows :
PROM-0 PROM-1 PROM-2 PROM-3 0000 07FF 0800 0FFF 1000 17FF 1800 1FFF A12 0 0 0 0 1 1 1 1 A11 0 0 1 1 0 0 1 1 A10 0 1 0 1 0 1 0 1 A9 0 1 0 1 0 1 0 1 A8 0 1 0 1 0 1 0 1 A7 A0 00 FF 00 FF 00 FF 00 FF

DESIGN MEMORY ADDRESS DECODER CONT

Common lines to all 4 chips A10 A0

lines that that used to select one of the four PROM

0 A12 A11

o o

C B A

0 1 2 74LS138 3 4 5 6 7

o o

PROM 0 : 0000H 07FFH PROM 1 : 0800H 0FFFH PROM 2 : 1000H 07FFH PROM 3 : 1800H 18FFH

o
o o o o o

DESIGN MEMORY ADDRESS DECODER CONT

Step 6 : Draw out the complete Memory Circuit.

EXERCISE
Memory Chip PROM 0 PROM 1 PROM 2 PROM 3 Capacity of Chip 2K x 8 6K x 8 4K x 8 8K x 8

Design Address Decoder using memory block below :