VLSI Design Course

Stick Diagram & Euler Path

Shy Hamami The VLSI Systems Center Ben-Gurion University Beer-Sheva, Israel

Stick Diagram
Stick diagrams are a design technique that represent the layout for a device They are used as an intermediary step between schematic and layout Here, the detailed layout design rules are simply neglected and the main features (active areas, polysilicon lines, metal lines) are represented by constant width rectangles or simple sticks They can save a lot of time in transistor placement and device minimization

VLSI Design Stick Diagram

Coloured Stick Diagram Notation

Silicon layers are typically colour coded as follows : diffusion (device well, local interconnect) polysilicon (gate electrode, interconnect) metal (contact, interconnect) contact windows N well (CMOS devices) This colour representation is used during mask layer definition Translation from circuit format to a mask layout (and vice-versa) is relatively straightforward

VLSI Design Stick Diagram

From Schematic to Stick Diagram

The schematic for a three input NAND gate looks like this: Notice how the transistors are arranged The three PMOS transistors are connected to power on one end and the output on the other The three NMOS transistors are connected in series with one connected to output and one connected to ground The inputs, A, B and C all connect to two transistors

VLSI Design Stick Diagram

From schematic to stick diagram (2)

Stick diagrams represent transistors by active to poly connections and active to metal connections To begin, you will need to draw a couple strips of active, one for PMOS transistors and one for NMOS transistors

VLSI Design Stick Diagram

From schematic to stick diagram (3)

Now draw a yellow well around the active that represents a p-type transistor and two horizontals blue lines to represent VDD and GND.

VLSI Design Stick Diagram

From schematic to stick diagram (4)

Refer back to the schematic, notice that every PMOS transistor is connected to V DD and an NMOS transistor connect to ground You should choose the upper blue line as VDD and the lower blue line as GND You might as well label them so that you keep this straight

VLSI Design Stick Diagram

From schematic to stick diagram (5)

Now create your gates by placing poly We will share diffusion regions so some of the drains are oriented up and some are oriented down. Notice that the gates of the n-type and p-type transistors are connected with poly.

VLSI Design Stick Diagram

From schematic to stick diagram (6)

Now its time to interconnect the device. You will probably have to experiment to find the best routing:

Notice that Poly and Metal 1 can overlap Avoid routing signals that are side by side for long lengths. This adds capacitance to the device. Avoid all interconnect overlap if possible. This adds capacitance to the device. Strive for simplicity. This will later provide the smallest and fastest devices. You can use Poly, Metal 2 (M2), and even Active to interconnect your device. But keep in mind, Poly and especially Active adds resistance to you device.

VLSI Design Stick Diagram

From schematic to stick diagram (7)

To finish the stick diagram, draw the connections between transistors, outputs, VDD and GND The final stick diagram should avoid unnecessary vias M1 can alternate in any direction M2 can be used for vertically straps

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From schematic to stick diagram

Following are some points to consider while drawing stick diagrams:

Make VDD and GND horizontal and have them stretch from the left to the right of the cells. This allows the cells to be abutted top to bottom or side by side by overlaying the power lines. It will be helpful to make all of your cells the same height (distance between power and ground) so they will line up better when they are abutted.

Keep your inputs and outputs inside the cell, and try to keep them on M1. M2 should be reserved for your select lines and clock. Data should flow in metal1 horizontally, and control should flow in M2 vertically. Clearly there will be times that this rule must be broken, but it will save a lot of confusion and hassle if you do all you can to follow this advice.

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From schematic to stick diagram

Following are some points to consider while drawing stick diagrams (cntd).

Use minimum Active. Fully use as much contact area as you have (unless you have a really good reason not to). Some of the Active contacts below are minimum size while they could clearly be larger!

Try to use shared Active regions. An example: Three transistors in series do not need the M1 and contacts between each of the gates and can all be on one piece of active as shown in the stick diagrams.

Where possible avoid crossing nets. In other words, don't take a M1 line, change to M2, cross M1, change back to M1 and so on. It is a big space waste to do this. Plan ahead and route the signals in a way where this is avoid as often as possible.
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Standard Cells
N Well VDD

Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects

In Out

Cell height is 12 pitch

Cell boundary

GND

Rails ~10

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Standard Cells
With minimal diffusion routing
VDD M2 In M1
GND GND VDD

With silicided diffusion

VDD

Out

In

Out

In

Out

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Complex CMOS Logic Gates

A B X = C (A + B) C A i B A B C GND X B i j A PDN

Logic Graph
C

X C

PUN

VDD

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Complex CMOS Logic Gates

Two Versions of C (A + B)

VDD

GND

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Complex CMOS Logic Gates

Consistent Euler Path

A simple method for finding the optimum gate ordering is the Eulerpath method The Euler path is defined as an uninterrupted path that traverses each edge (branch) of the graph exactly once Find a common Euler path for both graphs This results in uninterrupted active areas for NMOS as well as for PMOS transistors It may not always be possible to construct a complete Euler path both in the PD and in the PU network In that case, the best strategy is to find sub-Euler-paths in both graphs, which should be as long as possible This approach attempts to maximize the number of transistors which can be placed in a single, uninterrupted active area
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Complex CMOS Logic Gates

Euler Graph - Example

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Complex CMOS Logic Gates

Euler Graph Example (2)

Finding a common Euler path in both graphs for the PD and PU net Provides a gate ordering that minimizes the number of active-area breaks In both cases, the Euler path starts at (y) and ends at (z) The advantages of this new layout are more compact (smaller) layout area, simple routing of signals, and correspondingly, smaller parasitic capacitance.

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Complex CMOS Logic Gates

Euler Graph Example (3)

In this case, the separation between two neighboring poly columns must allow only for one metal-diffusion contact Note to the usage of M2 (not mandatory) The contacts of the active region can be arranged to give the employment of M1 only

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