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Design Hierarchy
Design Specification & Requirement Behavioral Design Register Transfer Level (RTL) Design Logic Design Circuit Design Physical Design Manufacturing
VHDL History
Initiated with VHSIC project in 1981 by DoD
VHSIC: Very High Speed Integrated Circuits
In 1983 DoD established requirements for VHSIC HDL (VHDL) In 1987 VHDL became an IEEE standard: VHDL 1076-1987 In 1993 a new version of VHDL released: VHDL 1076-1993
VHDL Specifications
Designing in Various Levels of Abstraction: from Behavioral to Gate Level Support for Design Hierarchy (Structural Design) Library Support Support of Generic Design Timing Control Concurrent & Sequential Statements Type Declaration ..
Components in VHDL
Each Component in VHDL is described as an ENTITY-ARCHITECTURE pair ENTITY part describes the interface of component ARCHITECTURE part describes the functionality and timing of component
An ENTITY may have different ARCHITECTURES, describing the component at various levels and with different details of timing and functionality
ENTITY Declaration
ENTITY entity_name IS generic clause port clause END ENTITY entity_name ;
ENTITY and3 IS GENERIC (delay: TIME := 5 ns); PORT (a, b, c : IN BIT; z : OUT BIT); END and3;
Ports
Ports are Component Interface Signals Each Port has:
Name Mode
IN OUT INOUT BUFFER : Input signals : Output Signals : Bidirectional Signals : Like OUT from outside the component & INOUT from Inside it
Type
Standard Types
Standard Package Types:
BIT BIT_VECTOR BOOLEAN INTEGER REAL TIME CHARACTER STRING
ARCHITECTURE Declaration
ARCHITECTURE arch_name OF entity_name IS architecture declarative part BEGIN concurrent statements END ARCHITECTURE arch_name ;
ARCHITECTURE single_delay OF and3 IS BEGIN z <= a AND b AND c AFTER delay ; END single_delay ;
Concurrent Statements
Concurrent Signal Assignment Component Instantiation Statement Generate Statement Process Statement Block Statement Concurrent Procedure Call Statement Concurrent Assert Statement
2:1 MUX
ENTITY Mux2x1 IS PORT (a0, a1, sel: IN BIT; z: OUT BIT); END Mux2x1; ARCHITECTURE conditional OF Mux2x1 IS BEGIN z <= a0 WHEN sel = 0 ELSE a1; END conditional;
VHDL Operators
Logical AND , NAND , OR , NOR , XOR , XNOR Relational = , /= , < , <= , > , >= Shift SLL , SRL , SLA , SRA , ROL , ROR Adding + , - , & Sign +,Multiplying * , / , MOD , REM Miscellaneous ABS , **
2:1 MUX
ARCHITECTURE selected OF Mux2x1 IS BEGIN WITH sel SELECT z <= a0 WHEN 0, a1 WHEN 1; -- a1 WHEN OTHERS; END selected;