Jaeger/Blalock

7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chapter 5
Bipolar Junction Transistors
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Chap 5 - 1
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chapter Goals
Explore physical structure of bipolar transistor
Understand bipolar transistor action and importance of carrier transport
across base region
Study terminal characteristics of BJT.
Explore differences between npn and pnp transistors.
Develop Transport and Ebers-Moll models for bipolar device.
Define four operation regions of BJT.
Explore model simplifications for each operation region.
Understand origin and modeling of Early effect.
Present SPICE model for bipolar transistor.Provide examples of worst-
case and Monte Carlo analysis of bias circuits.
Discuss bipolar current sources and current mirror.
Chap 5 - 2
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Physical Structure
Consists of 3 alternating layers of n- and
p-type semiconductor called emitter (E),
base (B) and collector (C).
Majority of current enters collector,
crosses base region and exits through
emitter. A small current also enters base
terminal, crosses base-emitter junction
and exits through emitter.
Carrier transport in the active base
region directly beneath the heavily
doped (n
+
) emitter dominates i-v
characteristics of BJT.
Chap 5 - 3
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Transport Model for npn Transistor
Narrow width of the base region
causes coupling between the two
back to back pn junctions.
Emitter injects electrons into base
region, almost all of them travel
across narrow base and are
removed by collector
Base-emitter voltage v
BE
and
base-collector voltage v
BC

determine currents in transistor
and are said to be positive when
they forward-bias their
respective pn junctions.
The terminal currents are
collector current(i
C
), base
current (i
B
) and emitter current
(i
E
).
Primary difference between
BJT and FET is that i
B
is
significant while i
G
= 0.
Chap 5 - 4
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
npn Transistor: Forward Characteristics
Forward transport current is

I
S
is saturation current
(
(
(

|
|
|
.
|

\
|
= = 1 exp
T
V
BE
v
S
I
F
i
C
i
A
9
10 A
18
10

s s

S
I
V
T
= kT/q =0.025 V at room temperature
Base current is given by
(
(
(

|
|
|
.
|

\
|
= = 1 exp
T
V
BE
v
F
S
I
F
F
i
B
i
| |
500 20 s s
F
|
Emitter current is given by
(
(
(

|
|
|
.
|

\
|
= + = 1 exp
T
V
BE
v
F
S
I
B
i
C
i
E
i
o
0 . 1
1
95 . 0 s
+
= s
F
F
F
|
|
o
is forward common-emitter
current gain
is forward common-
base current gain
In this forward active operation region,
F
B
i
C
i
| =
F
E
i
C
i
o =
Chap 5 - 5
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
npn Transistor: Reverse Characteristics
Reverse transport current is


(
(
(

|
|
|
.
|

\
|
= = 1 exp
T
V
BC
v
S
I
E
i
R
i
(
(
(

|
|
|
.
|

\
|
= = 1 exp
T
V
BC
v
R
S
I
R
R
i
B
i
| |
20 0 s s
R
|

Emitter current is given by
(
(
(

|
|
|
.
|

\
|
= 1 exp
T
V
BC
v
R
S
I
C
i
o
95 . 0
1
0 s
+
= s
R
R
R
|
|
o
is reverse common-emitter
current gain
is reverse common-
base current gain
Base current is given by
Base currents in forward and reverse modes
are different due to asymmetric doping levels
in emitter and collector regions.
Chap 5 - 6
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
npn Transistor: Complete Transport
Model Equations for Any Bias
|
|
|
|
|
.
|

\
|
(
(
(

|
|
|
.
|

\
|
|
|
|
.
|

\
|

|
|
.
|

\
|
= 1 exp exp exp
T
V
BC
v
R
S
I
T
V
BC
v
T
V
BE
v
S
I
C
i
|
|
|
|
|
|
.
|

\
|
(
(
(

|
|
|
.
|

\
|
|
|
|
.
|

\
|

|
|
.
|

\
|
+ = 1 exp exp exp
T
V
BE
v
F
S
I
T
V
BC
v
T
V
BE
v
S
I
E
i
|
|
|
|
|
|
.
|

\
|
(
(
(

|
|
|
.
|

\
|

|
|
.
|

\
|
+ = 1 exp 1 exp
T
V
BC
v
R
S
I
T
V
BE
v
F
S
I
B
i
| |
First term in both emitter and collector current expressions give current
transported completely across base region.
Symmetry exists between base-emitter and base-collector voltages in
establishing dominant current in bipolar transistor.
Chap 5 - 7
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Transport Model Calculations: Example
Problem: Find terminal voltages and
currents.
Given data: V
BB
= 0.75 V, V
CC
= 5.0
V, I
S
=10
-16
A, |
F
=50, |
R
=1
Assumptions: Room temperature
operation, V
T
=25.0 mV.
Analysis: V
BE
=0.75 V,
V
BC
= V
BB
- V
CC
=0.75 V-5.00V=-4.25 V
Evaluating the expressions for
terminal currents,
mA 07 . 1 =
C
I
mA 09 . 1 =
E
I
A 04 . 21 =
B
I
982 . 0
mA 09 . 1
mA 07 . 1
50
mA 0214 . 0
mA 07 . 1
= = =
= = =
E
I
C
I
F
B
I
C
I
F
o
|
Chap 5 - 8
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
pnp Transistor: Structure
Voltages v
EB
and v
CB
are positive when they forward bias their
respective pn junctions.
Collector current and base current exit transistor terminals and
emitter current enters the device.
Chap 5 - 9
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
pnp Transistor: Forward Characteristics
Forward transport current is


(
(
(

|
|
|
.
|

\
|
= = 1 exp
T
V
EB
v
S
I
F
i
C
i
Base current is given by
(
(
(

|
|
|
.
|

\
|
= = 1 exp
T
V
EB
v
F
S
I
F
F
i
B
i
| |
Emitter current is given by
(
(
(

|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
+ = + = 1 exp
1
1
T
V
EB
v
F
S
I
B
i
C
i
E
i
|
Chap 5 - 10
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
pnp Transistor: Reverse Characteristics
Reverse transport current is


(
(
(

|
|
|
.
|

\
|
= = 1 exp
T
V
CB
v
S
I
E
i
R
i
Base current is given by
(
(
(

|
|
|
.
|

\
|
= = 1 exp
T
V
CB
v
R
S
I
R
F
i
B
i
| |
Emitter current is given by
(
(
(

|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
+ = 1 exp
1
1
T
V
CB
v
R
S
I
C
i
|
Chap 5 - 11
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
pnp Transistor: Complete Transport
Model Equations for Any Bias
|
|
|
|
|
.
|

\
|
(
(
(

|
|
|
.
|

\
|
|
|
|
.
|

\
|

|
|
.
|

\
|
= 1 exp exp exp
T
V
CB
v
R
S
I
T
V
CB
v
T
V
EB
v
S
I
C
i
|
|
|
|
|
|
.
|

\
|
(
(
(

|
|
|
.
|

\
|
|
|
|
.
|

\
|

|
|
.
|

\
|
+ = 1 exp exp exp
T
V
EB
v
F
S
I
T
V
CB
v
T
V
EB
v
S
I
E
i
|
|
|
|
|
|
.
|

\
|
(
(
(

|
|
|
.
|

\
|

|
|
.
|

\
|
+ = 1 exp 1 exp
T
V
CB
v
R
S
I
T
V
EB
v
F
S
I
B
i
| |
Chap 5 - 12
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Operation Regions of Bipolar Transistor
Reverse Bias Forward Bias
Forward Bias Forward active region
(Normal active region)
(Good Amplifier)
Saturation region
(Not same as FET
saturation region)
(Closed switch)
Reverse Bias Cutoff region
(Open switch)
Reverse-active region
(Inverse active region)
(Poor amplifier)
Base-emitter junction Base-collector junction
Chap 5 - 13
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
i-v Characteristics of Bipolar Transistor:
Common-Emitter Output Characteristics
For i
B
=0, transistor is cutoff. If i
B
>0, i
C
also
increases.

For v
CE
> v
BE
, npn transistor is in forward active
region, i
C
= |
F
i
B
is independent of and v
CE.
For v
CE
< v
BE
, transistor is in saturation.

For v
CE
< 0, roles of collector and emitter
reverse.

Chap 5 - 14
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
i-v Characteristics of Bipolar Transistor:
Common-Base Output Characteristics
For v
CB
> 0, npn transistor is in forward active
region, i
C
=

i
E
is independent of and v
CE.

For v
CB
< 0, base-collector diode becomes
forward-biased and i
C
grows exponentially (in
negative direction) as base-collector diode
begins to conduct.

Chap 5 - 15
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
i-v Characteristics of Bipolar Transistor:
Common-Emitter Transfer Characteristic
Defines relation between collector current
and base-emitter voltage of transistor.
Almost identical to transfer characteristic
of pn junction diode
Setting v
BC
=0 in the collector-current
expression,
(
(
(

|
|
|
.
|

\
|
= 1 exp
T
V
BE
v
S
I
C
i
Chap 5 - 16
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Junction Breakdown Voltages
If reverse voltage across either of the two pn junctions in the transistor
is too large, corresponding diode will break down.
Emitter is most heavily doped region and collector is most lightly
doped region.
Due to doping differences, base-emitter diode has relatively low
breakdown voltage (3 to 10 V). Collector-base diode can be designed
to break down at much larger voltages.
Transistors must be selected in accordance with possible reverse
voltages in circuit.
Chap 5 - 17
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Early Effect and Early Voltage
As reverse-bias across collector-base junction increases, width of collector-
base depletion layer increases and width of base decreases (base-width
modulation).
In practical BJT, output characteristics have a positive slope in forward-
active region, collector current in not independent of v
CE
.
Early effect: When output characteristics are extrapolated back to point of
zero i
C
, curves intersect at common point v
CE
= -V
A
(Early voltage) which
lies between 15 V and 150 V.
Simplified equations (including Early effect):
(
(
(
(

(
(
(
(
(

+
|
|
.
|

\
|
=
A
V
CE
v
T
V
BE
v
S
I
C
i 1 exp
(
(
(
(

+ =
A
V
CE
v
FO F
1 | |
(
(
(
(
(

|
|
.
|

\
|
=
T
V
BE
v
FO
S
I
B
i exp
|
Chap 5 - 18
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
High Performane BJTs
Modern BJTs use combination of shallow and deep trench isolation
processes to reduce device capacitances and transit times.
Have polysilicon emitters, narrow bases or SiGe base regions.
SiGe transistors exhibit cutoff frequencies > 100 GHz.
Chap 5 - 19
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Biasing for BJT
Goal of biasing is to establish known Q-point which in turn establishes
initial operating region of transistor.
In BJT, Q-point is represented by (I
C
, V
CE
) for npn transistor or (I
C
, V
EC
)
for pnp transistor.
Q-point controls values of diffusion capacitance, transconductance,
input and output resistances.
In general, during circuit analysis, we use simplified mathematical
relationships derived for specified operation region and Early voltage is
assumed to be infinite.
The practical biasing circuits used for BJT are:
Four-Resistor Bias network
Two-Resistor Bias network
Chap 5 - 20
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Four-resistor biasing
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Four-Resistor Bias Network for BJT
2 1
1
R R
R
CC
V
EQ
V
+
=
2 1
2 1
R R
R R
EQ
R
+
=
E
I
E
R
BE
V
B
I
EQ
R
EQ
V + + =
A 68 . 2
6
10 23 . 1
V 7 . 0 - V 4
) 1 ( 000 , 16 7 . 0 000 , 12 4
=
O
=
+ + + =
B
I
B
I
F B
I |
A 201 = =
B
I
F C
I |
A 204 ) 1 ( = + =
B
I
F E
I |
V 32 . 4 = + =
=
|
|
|
|
|
.
|

\
|
C
I
F
F
R
C
R
CC
V
E
I
E
R
C
I
C
R
CC
V
CE
V
o
Q-point is (250 A, 4.17 V)
Chap 5 - 22
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Four-Resistor Bias Network for BJT
(contd.)
All calculated currents > 0, V
BC
= V
BE
- V
CE
= 0.7 - 4.32 = - 3.62 V
Hence, base-collector junction is reverse-biased, assumption of forward-
active region operation is correct.
Load-line for the circuit is:
C
I
C
I
F
F
R
C
R
CC
V
CE
V 200 , 38 12 = + =
|
|
|
|
|
.
|

\
|
o
The two points needed to plot the load
line are (0, 12 V) and (314 A,
0).Resulting load line is plotted on
common-emitter output characteristics.
I
B
= 2.7 A, intersection of corresponding
characteristic with load line gives Q-
point.
Chap 5 - 23
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Four-Resistor Bias Network for BJT:
Design Objectives
We know that



This implies that I
B
<< I
2
. So that I
1
= I
2
. So base current doesnt
disturb voltage divider action. Thus, Q-point is independent of base
current as well as current gain.
Also, V
EQ
is designed to be large enough that small variations in V
BE

assumed value of wont affect I
E
.
Current in base voltage divider network is limited by choosing
This ensures that power dissipation in bias resistors is < 17 % of total
quiescent power consumed by circuit and I
2
>> I
B
for |>50.
E
R
BE
V
EQ
V
E
R
B
I
EQ
R
BE
V
EQ
V
E
I

~

=
) (
BE
V
EQ
V
B
I
EQ
R <<
for
5 /
2 C
I I s
Chap 5 - 24
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Four-Resistor Bias Network for BJT:
Design Guidelines
Choose Thevenin equivalent base voltage

Select R
1
to set I
1
= 9I
B
.

Select R
2
to set I
2
= 10I
B
.


R
E
is determined by V
EQ
and desired I
C
.


R
C
is determined by desired V
CE
.
2 4
CC
V
EQ
V
CC
V
s s
B
I
EQ
V
R
9
1
=
B
I
EQ
V
CC
V
R
10
2

=
C
I
BE
V
EQ
V
E
R

~
E
R
C
I
CE
V
CC
V
C
R

~
Chap 5 - 25
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Four-Resistor Bias Network for BJT:
Example
Problem: Design 4-resistor bias circuit with given parameters.
Given data: I
C
=750 A, |
F
= 100, V
CC
= 15 V, V
CE
= 5 V
Assumptions: Forward-active operation region, V
BE
= 0.7 V
Analysis: Divide (V
CC
- V
CE
) equally between R
E
and R
C
.Thus, V
E
=5 V
and V
C
=10 V
k 67 . 6 =

=
C
I
C
V
CC
V
C
R
V 7 . 5
k 60 . 6
= + =
= =
BE
V
E
V
B
V
E
I
E
V
E
R
A 5 . 67 9
1
A 75 10
2

= =
= =
B
I I
B
I I
A 5 . 7
|
= =
F
C
I
B
I
k 124
10
2
k 4 . 84
9
1
=

=
= =
B
I
B
V
CC
V
R
B
I
B
V
R
Chap 5 - 26
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Two-Resistor Bias Network for BJT:
Example
Problem: Find Q-point for pnp transistor in 2-resistor bias circuit with
given parameters.
Given data: |
F
= 50, V
CC
= 9 V
Assumptions: Forward-active operation region, V
EB
= 0.7 V
Analysis:
V 18 . 2
V 88 . 2 ) ( 1000 9
mA 01 . 6 50
A 120
000 , 69
V 7 . 0 V 9
) 51 ( 1000 000 , 18 9
) ( 1000 000 , 18 9
=
= + =
= =
=
O

=
+ + =
+ + + =
EC
V
B
I
C
I
EC
V
B
I
C
I
B
I
B
I
B
I
EB
V
B
I
C
I
B
I
EB
V
Q-point is : (6.01 mA, 2.88 V)
Chap 5 - 27
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
BJT Current Mirror
Collector terminal of a BJT in forward-
active region mimics behavior of a
current source.
Output current is independent of V
CC
as
long as V
CC
> 0. Thus, BJT is in forward-
active region, since V
BC
=- V
CC
.
Q
1
and Q
2
are assumed to be matched
(with identical I
S,
|
F,
|
R,
V
A,
)
2 1 1 B
I
B
I
C
I
R
BE
V
BB
V
REF
I + + =

=
Chap 5 - 28
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
BJT Current Mirror (contd.)
With infinite |
FO
and V
A
, mirror ratio is unity. Finite current gain and Early
voltage introduce mismatch in output and reference current of mirror
(
(
(
(
(

(
(
(
(

(
(
(
(
(

|
|
.
|

\
|
+ +
|
|
.
|

\
|
=
T
V
BE
V
FO
S
I
A
V
CE
V
T
V
BE
V
S
I
REF
I exp 2
1
1 exp
|
FO A
V
BE
V
A
V
CE
V
REF
I
A
V
CE
V
T
V
BE
V
S
I
C
I
|
2
1
2
1
2
1 exp
2
+ +
+
= +
|
|
.
|

\
|
=
(
(
(
(

(
(
(
(
(

FO A
V
BE
V
A
V
CE
V
REF
I
O
I
|
2
1
2
1
MR
+ +
+
= =
Chap 5 - 29
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
BJT Current Mirror: Example
Problem: Find output current for given current mirror
Given data: |
FO
= 75, V
A
= 50 V
Assumptions: Forward-active operation region, V
BE
= 0.7 V
Analysis:
A 223
50
2
75
0.7
1
75
12
1
A) 202 ( MR.
A 202
k 56
V 7 . 0 V 12

=
+ +
+
= =
=

=
REF
I
O
I
R
BE
V
BB
V
REF
I
Chap 5 - 30
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
BJT Current Mirror: Altering Mirror
Ratio



Mirror ratio of BJT current mirror can be changed by changing relative
sizes of emitters in the transistors. For ideal case, mirror ratio is
determined only by ratio of the two emitter areas.
A
E
A
SO
I
S
I =
where I
SO
is saturation current of BJT with
one unit of emitter area: A
E
=1(A). Actual
dimensions of A are technology-dependent.
FO A
V
BE
V
A
V
CE
V
REF
I n
O
I
|
2
1
2
1
.
+ +
+
=
1
2
E
A
E
A
n=
Chap 5 - 31
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
BJT Current Mirror: Output Resistance
Current source using BJT doesnt have an output current that is
completely independent of terminal voltage across it, due to finite early
voltage. Current source seems to have resistive component with it.








R
o
is the small signal output resistance of the current mirror.
O
I
A
V
O
V
A
V
o
I
pt Q
o
v
o
i
o
R ~

+
=

c
c
=
(
(
(
(
(

|
|
|
|
|
.
|

\
|
1
1
FO A
V
BE
V
A
V
o
v
REF
I
FO A
V
BE
V
A
V
CE
V
REF
I
C
i
o
i
| |
2
1
1
2
1
2
1
2
+ +
+
=
+ +
+
= =
Chap 5 - 32
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Tolerances-Worst-Case Analysis:
Example
Problem: Find worst-case values of I
C
and V
CE
.
Given data: |
FO
= 75 with 50% tolerance, V
A
= 50 V, 5 % tolerance on
V
CC
, 10% tolerance for each resistor.
Analysis:
E
R
BE
V
EQ
V
E
I
C
I

= ~
To maximize I
C
, V
EQ
should be maximized,
R
E
should be minimized and opposite for
minimizing I
C
.
Extremes of R
E
are: 14.4 kO and 17.6 kO.
2 1
1
R R
R
CC
V
EQ
V
+
=
To maximize V
EQ
, V
CC
and R
1
should be
maximized, R
2
should be minimized and
opposite for minimizing V
EQ
.
Chap 5 - 33