Introduction to PIC Microcontroller

Munish Verma Astt. Prof., ECE Deptt. Haryana College of Technology & Management

Contents
Introduction to PIC Harvard Architecture & Pipelining Program Memory Considerations Register Pile Structure & Addressing Modes CPU Registers Instruction Set Simple operations

Introduction
Microcontrollers are small computer on a chip with some special properties: CPU, code memory, data memory and I/O ports all included on a single chip Dedicated to one task Small and low cost Embedded in many consumer devices PIC is Peripheral Interface Controller Why PIC is popular? (i) Speed (ii) Instruction set simplicity (iii) Integration of operational features (iv)Programmable timer options (v) Interrupt control (vi) Powerful output pin control (vii) I/O port expansion (viii)Serial programming via two pins (ix) EPROM/ OTP/ Rom options (x) PIC development tools

Family Core Architectural Differences

Baseline Core Devices (ex:12C50x, 16C5x) 12 bit wide code memory tiny two level deep call stack 33 instructions PIC10, PIC12 & PIC16 devices 6 pin to 40 pin packages.

Mid-Range Core Devices (ex:12C50x, 16C5x) 14 bit wide code memory 8 level deep call stack 35 instructions PIC12 and PIC16 devices Increased opcode width allows addressing of more memory

PIC17 High End Core Devices (Ex:17C4x,17C7xx) never became popular and superseded by the PIC18 architecture 16 bit wide opcode, 16 level deep call stack 58 instructions Packages of 40 to 68 pins a memory mapped accumulator read access to code memory (table reads), direct register to register moves, an external program memory interface to expand the code space an 8bit x 8bit hardware multiplier auto-increment/decrement addressing

Family Core Architectural Differences cntd

PIC18 High End Core Devices (ex:18Cxxx) New high end PIC architecture It inherits most of the features and instructions of the 17 series 77 instructions, much deeper call stack (31 levels deep) The call stack may be read and written Offset addressing mode A new indexed addressing mode in some devices

PIC24 and dsPIC 16 bit Microcontrollers Architectures differ significantly from prior models dsPICs are Microchip's newest family, digital signal processing capabilities Microchip's first inherent 16-bit (data) microcontrollers Hardware MAC (multiply-accumulate) Barrel shifting Bit reversal 16x16)-bit multiplication Other digital signal processing operations Can be efficiently programmed in C

PIC 16F877 Main components: ALU

Program memory Register file Program counter Status register Clock I/O ports Timers A/D converter USART

Architecture and Pipelining

PIC 16C6x /7x family uses Harvard architecture Exceptionally fast execution speed for a given clock rate

Instructions are fetched from program memory using 14-bit-wide memory bus and are different from buses used for accessing variables in data memory, I/O ports etc.

Pipelining
Processor executes each instruction during the

cycle following its fetch.

In pipelining, the overlapping of the execute cycle of one instruction with the fetch cycle of the next instruction leads to the execution of a new instruction every cycle.
This lockup progression is broken whenever an instruction includes a branch operation.

Program Memory Considerations

Each

member of PIC16C6x/7x family has either 2K or 4K addresses of program memory. A program memory of 2K addresses needs only an 11-bit program counter to access any address. A program memory of 4K addresses needs a 12-bit program counter. PIC family actually uses a 13-bit program counter ; allowing for extending the family to an 8K program memory without changing the CPU structure. For the 4K & 2K parts, the upper bit or bits are simply ignored during fetches from the program memory.

Program Memory Considerations

Two addresses in the program memory address space are treated in a special way by the CPU: (i) H000 goto Mainline instruction (ii) H004 goto IntService instruction Tables are assigned to address in the range H005 H0FF. Mainline program Mainline call Initial ;initialize everything Mainloop call Task1 ;deal with Task1 call Task2 ;deal with Task2 . . . call LoopTime ;force looptime to a fixed value goto MainLoop ; repeat

Register File Structure & Addressing Modes

register file is a PIC terminology used to denote the locations that an instruction can access via an address. consists of two components: (i) General-purpose register file : microcontrollers RAM (ii) Special-purpose register file: - i/p, o/p ports as well as control registers
- control bits - status bits

direct addressing mode indirect addressing mode

CPU Registers
7 0

Working register
7 0 6 0 5 4 3 2 1 0

STATUS (address H03 to H83) RP0 NOT_TO NOT_PD Z DC C Register bank select bit Reset status bit Reset status bit Zero bit Digit carry/ borrow bit Carry/borrow bit

FSR (address H04; H84) Indirect data memory add. pointer INDF (address H00; H80) accessing INDF accesses the location pointed to by FSR

CPU Registers contd

PCLATH (address H0A, H8A) Transferred by a write to PCL
12 8 7 0 4 0

Program Counter
PCL (address H02, H82)
12 0

Eight-level Stack

 bit-oriented and byte-oriented

Instruction Set

Complete Instruction Set Suggestions for writing assembly language code: Write instruction mnemonics in lowercase (e.g., xorwf) Write special register names , RAM variable names, and bit names in uppercase (e.g., STATUS, RP0) Write instruction and subroutine labels in mixed case (e.g., Mainline, Loop Time) Examples: Single-bit manipulation
bcf bsf clrw clrf PORTB, 0 STATUS, C ;clear bit 0 of PORTB ;set the carry bit ;clear the working register, W ;clear temporary variable TEMP1

Clear/move
TEMP1

Instruction Set
Clear/move
movlw 5 moclw 10 ;load 5 into W ;Load D10 or H10 or B10 into W ;depending upon default representation TEMP1 ;Move W into Temp1 TEMP1, W ;move TEMP1 into W TEMP1, F ;Swap 4-bit nibbles of TEMP1

movwf movf swapf

Increment/decrement/complement
incf TEMP1, F decf TEMP1, F comf TEMP1, F ;Increment TEMP1 ;Decrement TEMP1 ;Change 0s to 1s and 1s to 0s

Addition/Subtraction addlw 5 ;add 5 to W sublw 5 ;subtract