Chapter 1 The AVR Microcontroller and Embedded Systems Using Assembly and C

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com BIHE university
Introduction to Computing
Chapter 0
The AVR microcontroller and embedded systems

using assembly and c
AVR Microcontroller and Embedded System Using Assembly and C Mazidi, Naimi, and Naimi
2011 Pearson Higher Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Topics
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Internal organization of computers

The different parts of a computer
I/O Memory CPU
Connecting the different parts

Connecting memory to CPU Connecting I/Os to CPU
How computers work
Internal organization of computers

CPU Memory I/O

Input
E.g. Keyboard, Mouse, Sensor
Output
E.g. LCD, printer, hands of a robot
Memory
Everything that can store, retain, and recall information.

E.g. hard disk, a piece of paper, etc.
Memory characteristics
Capacity
The number of bits that a memory can store.
E.g. 128 Kbits, 256 Mbits
Organization
E.g. a 128 x 4 memory has 128 locations, 4 bits each
128 locations
How the locations are organized
4 bits
0 1 2
Access time
How long it takes to get data from memory
127
Semiconductor memories
ROM
Mask ROM PROM (Programmable
ROM)
RAM
)Static RAM( SRAM
)Dynamic RAM( DRAM Nonvolatile ( NV-RAM )RAM
EPROM (Erasable PROM) EEPROM (Electronic Erasable PROM) Flash EPROM
Memory\ROM\
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Mask ROM
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Programmed by the IC manufacturer
Memory\ROM\
PROM (Programmable ROM)

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OTP (One-Time Programmable)

You can program it only once
Memory\ROM\
EPROM (Erasable Programmable ROM)

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UV-EPROM
You can shine ultraviolet (UV) radiation to erase it Erasing takes up to 20 minutes The entire contents of ROM are erased
2764
Memory\ROM\
EEPROM (Electrically Erasable Programmable ROM)

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Erased Electrically
RDY/BSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
VCC WE NC
Erased instantly Each byte can be erased separately
8K x 8
A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
Memory\ROM\
Flash ROM
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Erased in a Flash the entire device is erased at once
Semiconductor memories
ROM
Mask ROM PROM (Programmable
ROM)
RAM
)Static RAM( SRAM
)Dynamic RAM( DRAM Nonvolatile ( NV-RAM )RAM
EPROM (Erasable PROM) EEPROM (Electronic Erasable PROM) Flash EPROM
Memory\RAM\
SRAM (Static RAM)

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Made of flip-flops (Transistors) Advantages:

Faster No need for refreshing
2K x 8
SRAM
Disadvantages:
High power consumption Expensive
Memory\RAM\
DRAM (Dynamic RAM)

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Made of capacitors Advantages:

Less power consumption Cheaper High capacity
Disadvantages:
Slower Refresh needed
Memory\RAM\
NV-RAM (Nonvolatile RAM)

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Made of SRAM, Battery, control circuitry Advantages:

Very fast Infinite program/erase cycle Non-volatile
Disadvantage:
Expensive
Internal parts of computers\CPU

Tasks:
It should execute instructions
It should recall the instructions one after another and execute them
Connecting memory to CPU

Memory pin out

VCC
GND 8 D0-D7 n A0-An-1
VCC
WE
OE CS
Writing to memory Reading from memory to CPU Connecting memory

Address Address CS CS OE Data Data WE WE Time Time

VCC
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GND 8 D0-D7
VCC
CPU
n A0-An-1 WE OE CS
Connecting I/Os to CPU

CPU should have lots of pins!
Mouse
Network
CPU
Keyboard
Graphic Card
Sound Card
Connecting I/Os to CPU using bus

Address bus
Data bus
Control bus Read
Write
CPU
I/O 0
I/O 1 I/O 2 I/O n
Connecting I/Os and Memory to CPU

Address bus Data bus Control bus Read

Write
CPU
n 8
I/O 0
VCC
I/O 1
I/O 2
I/O n
GND A0-An-1 D0-D7
VCC
WE OE CS
Connecting I/Os and memory to CPU using bus

VCC
0 1 2
How could we manage it?

A0-An-1 GND D0-D7
WE
OE
Address bus
Data bus
Write Control bus Read
CPU
I/O 0 I/O 1
I/O 2 I/O n
CS
Connecting I/Os and Memory to CPU using bus (Peripheral I/O)

VCC
0 1 ..
A0-An-1
GND
D0-D7
63
WE
OE
Address bus
Data bus
Write Read Control bus IO/MEM
CPU
I/O 0 I/O 1
I/O 2 I/O n
CS
Connecting I/Os and Memory to CPU using bus (Memory Mapped I/O)
0 1 ..
A0-An-1
GND
D0-D7
WE
OE
How could we make the logic circuit?
15
The logic circuit enables CS when address is between 0 and 15
VCC
Logic circuit
Address bus
Data bus Solution

Write Control 1. bus Write the address range in binary Read 2. Separate the fixed part of address 3. Using a NAND, design a logic circuit whose output activates when the fixed address is given to it.
CPU
From address 0 0 0 0 0 0 0 0 0 I/O 16 To address15 0 0 0 0 1 1 1 1
a7 a6 a5 a4 a3 a2 a1 a0
I/O 17
a4 I/O a5 18 a6 a7
CS
I/O n CS
Another example for address decoder

Design an address decoder for address of 300H to 3FFH.

Solution 1. Write the address range in binary 2. Separate the fixed part of address 3. Design the logic circuit.
From address 300H 0 0 1 1 0 0 0 0 0 0 0 0 To address 3FFH 001111111111

An easy way of designing
a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
a8 a9 a10 a11
CS
Inside the CPU

PC (Program Counter) Instruction decoder ALU (Arithmetic Logic Unit) Registers

PC ALU A B
CPU
Instruction decoder
C D
registers
How computers work

0 1
31h 31 C4h 26h 81h EAh 0h 5h
VCC
2 3 4 5
A [17] BA A [6] AA+B [7]A
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A0-An-1
GND
D0-D7
WE
OE
Address bus Data bus

Logic circuit
ALU
CPU
PC:
1 0
A B C
D
Inst. Dec.
registers
I/O 16
I/O 17
CS
I/O 18
I/O n
How computers work

0 1
31h C4h 26h 81h EAh 0h 5h
VCC
2 3 4 5
A [17] BA A [6] AA+B [7]A
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A0-An-1
GND
D0-D7
WE
OE
Address bus 17 Data bus

Logic circuit
ALU
CPU
PC:
1
31
A B C
9
D
Inst. Dec.
registers
I/O 16
I/O 17
CS
I/O 18
I/O n
How computers work

0 1
31h C4 C4h 26 26h 81h EAh 0h 5 5h
VCC
2 3 4 5
A [17] BA A [6] AA+B [7]A
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A0-An-1
GND
D0-D7
WE
OE
6 Address bus 17
Logic circuit
Data bus
ALU
CPU
PC:
1 2 3
9 A B
D
Inst. Dec.
registers
I/O 16
I/O 17
CS
I/O 18
I/O n
How computers work

0 1
31h C4h 26h 81 81h EA EAh 0h 5h
VCC
2 3 4 5
A [17] BA A [6] AA+B [7]A
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A0-An-1
GND
D0-D7
WE
OE
Address bus Data bus

+
E
7
Eh
Logic circuit
ALU
CPU
PC:
4 3 5
A 9 B C
E 5
D
Inst. Dec.
registers
I/O 16
I/O 17
CS
I/O 18
I/O n
How Instruction decoder works

Opcode
Operand Instruction
Opcode
Operand
Instruction
Operation Code 000
0011 0001
1100 0100 0010 0110 1000 0001 1110 1010 0000 0000 0000 0101 0 1 2 3 4 5 6 7 31h C4h 26h 81h EAh 0h 5h
Meaning Ax A [x] A A register (x) AA+x
A [17] BA A [6] AA+B [7]A
001 010 011
100
101 110 111
A A + register (x)
AAx Register (xH) Register (xL) [x] A
Von Neumann vs. Harvard architecture

Code Memory
Data bus Address bus Control bus

CPU
Data bus Address bus Control bus

Data Memory
Von Neumann architecture
Code Memory
Data Memory
Data bus
CPU
Address bus Control bus
Harvard architecture

Chapter 1 The AVR Microcontroller and Embedded Systems Using Assembly and C

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Chapter 1 The AVR Microcontroller and Embedded Systems Using Assembly and C

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Formate disponibile

www. Micro Digital Ed.

com BIHE university

The AVR microcontroller and embedded systems

Internal organization of computers

Connecting the different parts

How computers work

Internal organization of computers

CPU Memory I/O

Everything that can store, retain, and recall information.

How the locations are organized

EPROM (Erasable PROM) EEPROM (Electronic Erasable PROM) Flash EPROM

Programmed by the IC manufacturer

PROM (Programmable ROM)

OTP (One-Time Programmable)

EPROM (Erasable Programmable ROM)

EEPROM (Electrically Erasable Programmable ROM)

www. Micro Digital Ed. com

RDY/BSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS

Erased instantly Each byte can be erased separately

A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3

Erased in a Flash the entire device is erased at once

EPROM (Erasable PROM) EEPROM (Electronic Erasable PROM) Flash EPROM

SRAM (Static RAM)

Made of flip-flops (Transistors) Advantages:

DRAM (Dynamic RAM)

Made of capacitors Advantages:

NV-RAM (Nonvolatile RAM)

Made of SRAM, Battery, control circuitry Advantages:

Internal parts of computers\CPU

Connecting memory to CPU

Memory pin out

GND 8 D0-D7 n A0-An-1

Writing to memory Reading from memory to CPU Connecting memory

Address Address CS CS OE Data Data WE WE Time Time

Connecting I/Os to CPU

CPU should have lots of pins!

Connecting I/Os to CPU using bus

Connecting I/Os and Memory to CPU

Address bus Data bus Control bus Read

GND A0-An-1 D0-D7

Connecting I/Os and memory to CPU using bus

How could we manage it?

Connecting I/Os and Memory to CPU using bus (Peripheral I/O)

How could we make the logic circuit?

The logic circuit enables CS when address is between 0 and 15

Data bus Solution

From address 0 0 0 0 0 0 0 0 0 I/O 16 To address15 0 0 0 0 1 1 1 1

Another example for address decoder

Design an address decoder for address of 300H to 3FFH.

From address 300H 0 0 1 1 0 0 0 0 0 0 0 0 To address 3FFH 001111111111

Inside the CPU

PC (Program Counter) Instruction decoder ALU (Arithmetic Logic Unit) Registers

How computers work

31h 31 C4h 26h 81h EAh 0h 5h

A [17] BA A [6] AA+B [7]A

Address bus Data bus

How computers work

31h C4h 26h 81h EAh 0h 5h

A [17] BA A [6] AA+B [7]A

Address bus 17 Data bus

How computers work

31h C4 C4h 26 26h 81h EAh 0h 5 5h

A [17] BA A [6] AA+B [7]A