Design for Testability

(03)5773693#157

jbchen@cic.org.tw

Chip Implementation Center (CIC) National Applied Research Laboratories Hsinchu, Taiwan

Agenda
Logic Testing
Basic Concept Design for Testability RTL Rule Checker DFT Guidelines and Rules Synopsys DFT Design Flow

Memory Testing
Basic Concept Memory BIST SynTest SRAMBIST Flow

Chapter 1

Logic Testing

Basic Concept

What is Testing
Testing is a process of determining whether a device is good (function correctly) or not
Testing includes test pattern generation, application and output evaluation
Apply Input (Stimulus) Test Pattern Compare Output (Response)

DUT

Why Testing
In order to guarantee the product quality, reliability, performances, etc.
Cost is the most important. The rule of ten

Defect detected during IC testing

Defect detected during system testing

Defect detected during field testing

Simplified IC Production Flow

Layout Design Specification

Process

Wafer

Probe Test

Final Test

Marking

Packaging

QA Sample Test

Shipping

Verification v.s. Test (1/2)

Design verification ensures design matches intent
Manufacturing test ensures parts are manufactured correctly How is manufacturing test performed ?
Test Pattern (Test Problem)
Tester (ATE) Fail

Good Device Under Test (DUT)

Verification v.s. Test (2/2)

Design Synthesis Manufacture

always @(a or b) begin c = a & b end

Verification

Verification

Test

Diagnosis
9

Automatic Test Equipment

Tester (ATE)
Key features to be aware of
Number of pins

Number of clocks
Frequency Accuracy Precision Number of scan channels Amount of memory Vector application formats

10

Type of Testing
On Wafer Test
Characterization Test Production Test

Burn-In Test
Diagnostic Test

11

Test Items
Function Test Verify functionality
Structural Test Verify manufacturability Parametric Test Verify AC and DC parameters

At-Speed Test Verify performance

Leakage Test Defects may cause high leakage current
12

Pins/Gates

TTL logic allowed easy access to individual gates.

1.E+08

Transistors

1.E+07

Pins / Gates << 0.001 Hard to access to a chip.

1.E+06
1.E+05 1.E+04

386 286 8080

1970 1974 1978 1982 1986 1990

Pentium 486

1998

Year

1994

2002

1.E+03

13

What is Fault & Fault Model

Fault is a physical defect in a circuit or system
Fault model is the logical effect of a fault (physical defect)
Reduce the test complexity Independent of technology
POWER
Output Shorted to 1

Input Open

A U1 Y B
Stuck-At-0 (U1/Y SA0)

IN
Input Shorted to 0

OUT

GROUND

14

Yield & Fault Coverage

Yield (Y) is the ratio of the number of good dies per wafer to the number of dies per wafer
Y = (# of good dies) / (# of all dies) Fault coverage (FC) is the measure of the ability of a test set to detect a given class of faults that may occur on the device under test (DUT) FC = (# of detected faults) / (# of possible faults)

15

Defect Level & Fault Coverage

Defect level (DL) is the fraction of devices that pass all the tests and are shipped but still contain some faults
DL = 1-Y(1-FC)

[Williams and Brown 1981]

Defect level is measured in terms of DPM (detects per million), and typical requirement is less than 200 DPM i.e. 0.02 %
DL = 200 DPM

Y (%)

10

50

90 99.8

95 99.6

99 98
16

FC(%) 99.99 99.97

Defect Level & Quality

Chip Defect Level (DPM)
10,000

Y = 50% Y = 90%

Board Failing Probability (%)

90 80

1,000

70 60 50 40 30 20 10 0 10,000 1,000 100 40 Chips 200 Chips

100

10
99.99 99.9 99 90

Fault Coverage

Defect Level (DPM)

Data Source: Prof. Ed. McCluskey 1988, 1998

High fault coverage minimizes DPM

High fault coverage is imperative when yield is low

17

The Testing Problem

Given a set of faults in a device under test (DUT), how to obtain a small number of test patterns which detects high fault coverage ?
What faults to test ? (fault modeling)
How are the test patterns obtained ? (test pattern

generation) How is the test quality (fault coverage) measure ? (fault simulation) How are test patterns applied and results evaluated ? (ATE/BIST)

18

Fault Model (1/3)

Single stuck-at fault
A line (gate input/output) in the circuit is fixed at

logic 0 or logic 1 and independent of other signal values

Stuck-At-1 (U0/A SA1)

A U1 Y B
Stuck-At-0 (U1/Y SA0)

A U0 B Y

19

Fault Model (2/3)

Multiple stuck-at fault
several stuck-at faults occur at the same time

Bridging fault
Two or more normally distinct adjacent lines are

shorted together

Other fault models Single stuck-at fault is the most popular

reduce the complexity of testing single stuck-at fault cover a lot of multiple stuck-at

fault

20

Fault Model (3/3)

5% 95 %

Good

Fail

Fault Model

21

Fault Simulation (1/2)

To evaluate the quality of a test set
i.e. to compute its fault coverage

Reduce the time of test pattern generation

A pattern usually detected multiple faults
Fault simulation is used to compute the faults

accidentally detected by a particular pattern

To generate fault dictionary

For post test diagnosis

To analyze the reliability of a circuit

22

Fault Simulation (2/2)

Patterns (Sequences) (Vectors)

Faulty Circuit #1 (B/0)

Response Comparison

Fault-free Circuit Primary Inputs (PIs) A B C D Primary Outputs (POs)

Detected?

23

Test Pattern Generation

TA/0={10}, TA/1={00}
TB/0={01}, TB/1={00} TY/0={01}or{10}or{11},TY/1={00}
A U1 B
Y Stuck-at-0; Y s/0; Y/0

T= {00,01,10}
A 0 0 1 1 B 0 1 0 1 Y 0 1 1 1 Y(A/0) Y(A/1) Y(B/0) Y(B/1) Y(Y/0) Y(Y/1) 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1
24

Fault Coverage (Example)

A U1 B
Y Stuck-at-0; Y s/0; Y/0

Test Pattern (A,B) {(0,0)} {(0,1)} {(1,1)} {(0,0),(0,1),(1,0)}

Faults Detected A/1, B/1, Y/1 B/0, Y/0 Y/0 all

FC 3/6= 50% 2/6=33.33% 1/6=16.67% 6/6= 100%

Functional test need four pattern => reduce test cost

25

Test Pattern Generation (1/5)

Path-oriented Techniques
D-algorithm Step 1. Target a specific stuck at fault

D
SA0

C B A

26

Test Pattern Generation (2/5)

Fault activate
Step 2. Drive the fault site opposite value D: 1/0 D: 0/1
Fault-Free Logic Faulty Logic

D
SA0

1/0

C B A

1 /0
D

27

Test Pattern Generation (3/5)

Back tracing (controllability)
Step 3. Specify inputs value to generate the

appropriate value at fault site

D
SA0

C B A

1 /0
D

28

Test Pattern Generation (4/5)

Fault propagation (observability)
Step 4. Select a path from the fault site to the

primary output

D C B A

1 SA0 0 1 /0
D

1/0 D
D

0/1

29

Test Pattern Generation (5/5)

Line justification
Step 5. specify all other inputs

Fault detection
If Z(T)faulty differs from Z(T)good

1 SA0 0

1/0

D D

C
B A

1 /0
D

0/1

1 X 1 Discrepancy
30

Test Pattern T

Automatic Test Pattern Generation

Goal
Generate the test patterns for target fault model

and keep the number of test pattern as small as possible

How ?
Computer-Aided-Design Tools

Fault list

Test Generation

Fault Simulation

Remove all detected fault and select next fault

Test Set

Add pattern to test set

31

Fault Equivalence
A set of faults is equivalent if no test pattern exists to tell them apart.
The function under these faults is equivalent for any input combination A/1
Y/1 B/1

A 0 0 1 1

B 0 1 0 1

Y 0 1 1 1

Y(A/0) Y(A/1) Y(B/0) Y(B/1) Y(Y/0) Y(Y/1) 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1

32

Fault Collapsing
By testing for only one fault per equivalence set, we can greatly reduce (or collapse) the fault universe
Speed up fault simulation
A/0

Y/0
B/0 Y/1

33

Untestable fault
A fault cannot be excited and/or propagated
Untestable fault is caused by a redundant design of the DUT, that is the line and the associate gate can be removed without changing the logic function of the DUT Untestable fault is also called as redundant fault F=ab+ab+bc F=ab+ab
a b a c 1 b 1 c
0

f s-a-0

34

Sequence Logic is Harder to Test

Testing requires a sequence of test vectors
Requires initialization of the machine, which may be difficult
Long initialization sequence

Invalid state justification

Faults may cause increasing of internal states

SA0 occurs at here
1
0 1

Observe/Verify output at PO

Apply test input at PI and set value here to test SA0

35

Sequence ATPG
Time-frame Expansion
Primary inputs Combinational Logic Primary inputs PseudoPIs Combinational Logic PseudoPOs

Primary outputs present state

F/F

Primary outputs next state

Sequential circuit model

A single time-frame

Cost Issue: For large sequential logic blocks with complex circuits, sequential ATPG is just not practical.
36

Design for Testability

37

Design for Testability (1/2)

The design technologies which make test generation and diagnosis easier
Testability = controllability + observability DFT Methods
Ad-hoc methods Scan, full and partial

Built-In Self-Test (BIST)

Boundary scan

38

Design for Testability (2/2)

No single DFT technique solves all VLSI testing problems
No single DFT technique is effective for all kinds of circuits No DFT approach is free
Manpower and tool costs Area overhead and performance penalty

39

Scan Design (1/2)

Provide controllability and observability at internal flip-flops for testing
Method
Add scan enable control signal(s) to circuit Connect flip-flops to form shift registers in test

mode Make inputs/outputs of the flip-flops in the shift register controllable and observable

Types
Internal scan Full scan Partial scan Boundary scan
40

Scan Design (2/2)

Primary Input
Mode Switch (normal or test) scan_en Scan In
1. 2. scan_en=1, shift in the scan pattern (clk trig.) scan_en=0, apply pattern in PI, CL evaluates the response (clk not trig.) scan_en=0, observe the PO (clk not trig.) scan_en=0, capture the response (clk trig. once) first scan out scan_en=1, shift out response (clk trig.)

Primary Output
Combinational Logic

FF

FF

3. 4.

FF Scan Out
41

5.

Scan Test Waveform (1/2)

Test CLK

Scan Enable

Test Mode Scan in Scan in and scan out Scan out

42

Scan Test Waveform (2/2)

Test CLK Scan Enable

First scan out PPO capture PI ready PO compare

Shift out response Shift in pattern

43

Impact of Scan Design

If you plan to insert internal scan, you must account for the impact of scan registers on a chip early in the design flow!
Larger area than non-scan registers; (Area overhead) Larger setup time requirement. (Timing impact)
TI TI DI TE CLK
1 0 1

DO

DI

CLK

Multiplexed Scan Register Chain

Non-Scan Register

Additional pin overhead

44

Why DFT ?
Product quality
Reduce field returns (Defect Level) Improve yield

Test cost
Reduce the complexity of test generation Reduce the cost of testing

45

DFT Tools
Synopsys
LEDA DFT Compiler TetraMAX BSD Compiler

Mentor
DFTAdvisor FastScan

BSDArchitect
LBISTArchitect

SynTest
TurboCheck-RTL TurboCheck-Gate TurboScan TurboBSD

TurboFault
46

RTL Rule Checker

47

Why RTL Rule Checker?

Motivation
Early identification of RTL design errors. Reusability of RTL code. Testability of RTL code. Fast iteration process

48

Synopsys LEDA
Features
Check for syntatic/semantic, coding style for

synthesis DFT rules check RMM rules check Many Synopsys tools (DC,VCS,Formality ) Report the file name and line number of problematic code Support User defined rule

49

SynTest TurboCheck-RTL
Features
Lint capability ( more than 400 rules) Check for syntatic/semantic, coding style for synthesis DFT rules check (more than 40 rules) RMM rules check Report the file name and line number of

problematic code Support User defined rule

50

DFT Guidelines and Rules

51

DFT Guideline for Combinational Logic

Partition large circuit into small one
Avoid gates with large fan-in

Disable one-shots, mono-stables circuit during testing

Delay element

One-shot

52

DFT Guideline for Combinational Logic

Avoid combinational feedback loops
A B Q

Avoid redundancy Provide test points to enhance controllability and observability

53

DFT Guideline for Sequential Logic

Make flip-flops initializable
Disable internal oscillators and clocks Make latch transparent under test

54

DFT Guideline for Scan Architecture

No clocks used as data i.e. pulse generator
No data used as clock i.e. ripple counter No flip-flops are non-scanned

Control test mode and scan enable signal directly

Replace tri-state buses by multiplexers to avoid bus contention
Ena
ENB

O
ENB

55

DFT Guideline for Scan Architecture

Feed all inputs and outputs of embedded memory to scannable flip-flops
Scan enable should be routed as clock-tree Balance the scan chains
Un-observable

Scan register

Scan register

Logic

Logic

Logic

Memory

Memory

Un-controllable
56

Logic

DFT Rule Violations

Generated clock (gated clock)
Generated set/reset Combinational loop

Bi-direction
Tri-state Latch Cross clock domain Constant or Floating signal

57

How to Fix DFT Rule Violations

Add a new signal TestMode
TestMode =1b0 for normal function TestMode =1b1 for test
TestMode Extra Signal

Introduce Extra Signal Set to Constant Value

TestMode

TestMode

Set to 0

Set to 1
58

DFT Rule Violation (1/6)

Generated clock (gated clock)
D CLK EN Q

Combinationally gated clocks

Sequentially gated clocks

CLK

Logic gates

Generated gated clocks

Generated CLK

Primary Input

59

DFT Rule Violation (2/6)

Generated set/reset (Asynchronous set/reset)
D Q

Combinationally gated set/reset

CLR

Sequentially gated set/reset

CLR

CLR

60

DFT Rule Violation (3/6)

Pulse generator
Q

Combinational feedback loop

A B Q

Potentially combinational feedback loop

EN A B Q

61

DFT Rule Violation (4/6)

Tri-state contention
Ena
ENB

O
ENB

Bi-direction
Force one direction
Enable

Latch
Make latch transparent

62

DFT Rule Violation (5/6)

Floating primary input/output
Floating primary bi-directional port Floating input/output

Floating net
Inaccessible memory objects
A memory object is inaccessible if there is no path

existed from the memory object to any one of primary output port, and if it is not in the scan chain.

63

DFT Rule Violation (6/6)

Cross clock domain
Add lockup latch
Cross clock D CLK 1 D Q Q

CLK 2

64

Synopsys DFT Design Flow

65

Synopsys DFT Compiler Flow

compile -scan
ScanReady Synthesis

check_test
Pre-Scan DRC

insert_scan
Insert Scan

check_test
Post-Scan DRC Preview Coverage

HDL

Constraints: Scan style, speed, area

Technology Library: Gates, flip-flops, scan equivalents

Constraint-Based Scan Synthesis: Routing, balancing, gate-level optimization

66

Scan-Ready Synthesis
HDL Code compile -scan technology library DFTC

TI DI DFF DO DI

1 0

TO

DO
DFF

67

Pre-Scan Check
Check gate-level scan design rule before scan chain synthesis.
Looks at four categories of testability issues:
Modeling problems, such as lack of a scan equivalent.

Topological problems, like unclocked feedback loops.

Protocol inference, such as test clocks and test holds. Protocol simulation, to verify proper scanning of bits.
dc_shell> check_test ...basic checks... ...checking combinational feedback loops... ...inferring test protocol... Inferred system/test clock port CLK (45.0,55.0). ...simulating parallel vector...simulating serial scan-in Information: The first scan-in cycle does not shift in data.(TEST-301) Warning: Cell U1 (FD1S) is not scan controllable. (TEST-302) Information: Because it clocks in an unknown value from pin TI.(TEST-512) Information: Because port SI is unknown. (TEST-514) Information: As a result, 3 other cells are not scan controllable.(TEST-502) Information: Test design rule checking completed. (TEST-123)

68

Scan Chain Insertion

Scan-Chain Insertion Algorithm:
1. Targets the previewed scan-path architecture. 2. Performs any remaining scan replacements. 3. Adds disabling/enabling logic to tristate buses. 4. Conditions the directionality of bidirectional ports. 5. Wires the scan flops into the specified chains. 6. Optimizes the logic, minimizing constraint violations.
insert_scan -map_effort medium

69

Post-Scan Check
Why run check_test again?
Confirm there are no new DFT problems. Verify the scan chains synthesized operates

properly. Create an ATPG-ready database.

check_test

70

Estimate Test coverage

Use the DFTC ATPG command: estimate_test_coverage will call TetraMAX for fault estimate.
estimate_test_coverage
Pattern Summary Report Uncollapsed Stuck Fault Summary Report ----------------------------------------------fault class code #faults ------------------------------ ---- --------Detected DT 3084 Possibly detected PT 0 Undetectable UD 12 ATPG untestable AU 0 Not detected ND 0 ----------------------------------------------total faults 3096 test coverage 100.00% ----------------------------------------------Information: The test coverage above may be inferior than the real test coverage with customized protocol and test simulation library.

71

AutoFix and Shadow LogicDFT

By default, the AutoFix and Shadow LogicDFT utilities are disabled.
To use AutoFix, you enable the utility and specify the scope of the design on which it will apply.
set_dft_configuration -order {autofix} set_dft_configuration -order {wrapper} set_dft_configuration -order {autofix,wrapper}

72

AutoFix and Shadow LogicDFT

To use AutoFix and Shadow LogicDFT, we need to change our command from scan to dft.
compile -scan check_scan preview_scan insert_scan report_test set_scan_configuration set_scan_signal compile -scan check_dft preview_dft insert_dft report_test -dft set_dft_configuration set_dft_signal

73

scan_out

Scan Registers

Un-controllable

Block Box

Un-observable

scan_in

Scan Registers

Black Box

74

scan_out

Scan Registers

Shadow LogicDFT

controllable

Wrapper Black Box

Wrapper observable

scan_in

Scan Registers

75

DFT Compiler to TetraMAX

Write f verilog hierarchy \ output design_dft.v read netlist design_dft.v

design_dft.v

DC

Simulation Library

TetraMax read netlist library.v

Write_test_protocol f stil \ out design.spf

design.spf

run drc design.spf

Simulation ATE Vectors Testbenches

Fault Reports

76

Synopsys TetraMAX Flow

4

5
BEGIN Review Result

1
Library

Design

Run ATPG

6 3 2
Run DRC Compress & Save Patterns

Build Model

DRC Procedures

DONE

77

Chapter 2
Memory Testing

78

Basic Concepts

79

Introduction
Memory is the key component in electronic system
Embedded memory is one of the most universal block in a SoC Embedded memory testing is a more and more difficult problem
I/O pins limited Speeds

BIST is considered as the best solution

80

Type of Memory Test

Parametric Test: DC & AC
Reliability Screening
Long-cycle testing Burn-in: static & dynamic BI

Functional Test
Device characterization Failure analysis Fault modeling Simple but effective Test algorithm generation Small number of test patterns (data backgrounds) High fault coverage Short test
81

RAM Functional Fault Model (1/3)

Stuck-At Fault (SAF)
Cell or line stuck-at 0/1

Transition Fault (TF)

Cell fails to transit from 0 to 1 or 1 to 0

Address-Decoder Fault (AF)

No cell accessed by a certain address

Multiple cells accessed by certain address

Certain cell not accessed by any address Certain cell accessed by multiple address

82

RAM Functional Fault Model (2/3)

Coupling Fault (CF)
State Coupling Fault (CFst) Coupled (victim) cell is forced to 0 or 1 if coupling (aggressor) cell is in given state Inversion Coupling Fault (CFin) Transition in coupling cell complements (inverts) coupled cell Idempotent Coupling Fault (Cfid) Coupled cell is forced to 0 or 1 if coupling cell transits from 0 to 1 or 1 to 0

83

RAM Functional Fault Model (3/3)

Stuck-Open Fault (SOF)
Cell cant access due to broken line

Bridging Fault (BF)

Short between cells (AND Type or OR Type)

Other Faults

84

RAM Test Algorithm

A test algorithm is a finite sequence of test elements
A test element contains a number of memory

operations
Data patterns (backgrounds) Address (sequence)

A march test is a finite sequence of march elements

A march element is specified by an address order

and a number of read/write operations {(w1,r1); }

85

Default Test Algorithms

Moving Inversion (MOVI) Algorithm [De jonge & Smeulders 1976]
{(w0); (r0,w1,r1);(r1,w0,r0);(r0,w1,r1); (r1,w0,r0);} Test length (13N) Target faults:AF, SAT, TF and most CF

86

Test Algorithm (Example)

March C- [Goor 1991]
{w(0); (r0,w1); (r1,w0); (r0,w1); (r1,w0);(r0)} Test length: 10 N Target faults:AF, SAT, TF and all CF

87

Test Algorithm Summary (1/2)

Fault coverage Algorithm

SAF
MATS MATS+ MATS++ MARCH X All All All All

AF
Some All All All

TF

CFin CFid CFst Length

4N 5N

All All All

6N 6N

MARCH C-

All

All

All

All

All

All

10N
88

Test Algorithm Summary (2/2)

Algorithm MATS MATS+ MATS++ MARCH X Description
{w(0);(r0,w1);(r1)} {w(0);(r0,w1);(r1,w0)} {w(0);(r0,w1);(r1,w0,r0)} {w(0);(r0,w1);(r1,w0);(r0)}

Ref [1] [2] [3] [3]

MARCH C- {w(0);(r0,w1);(r1,w0);(r0,w1);(r1,w0);(r0)} [4]

89

How to detect faults?

Algorithm: MATS+
Cell (2,1) SA0 0 0 0 0 0 0 0 0 0
After M0
Bad Memory

{w(0);(r0,w1);(r1,w0)}

Good Memory

1 1 1 1 1 1 1 1 1
After M1

0 0 0 0 0 0 0 0 0
After M2

0 0 0 0 0 0 0 0 0
After M0

1 1 1 0 1 1 1 1 1
After M1

0 0 0 0 0 0 0 0 0
After M2
90

Word-Oriented RAM
Background bit is replaced by background word
For example: 8bit memory
Background 0 ->

(00000000,01010101,00110011,00001111) Background 1 -> (11111111,10101010,11001100,11110000)

91

Memory BIST

92

Memory BIST Tools

Synopsys
DesignWare SRAM BIST MacroCell RAM coreConsultant GUI Gate-level

SynTest
TurboBIST-Memory ROM, RAM Edit a memory spec. file RTL

93

Memory BIST Tools

Mentor
MBISTArchitect ROM, RAM Edit a memory spec. file RTL

94

Memory Built-In Self-Test

Original Memory Port Memory Wrapper

Mux
BistMode

Memory

BIST Controller

mem_ctrl bist_ctrl Q

Analyzer

BistFail ErrorMap Finish

95

SynTest Memory BIST Architecture

Original memory port

mem_ctrl BIST Controller BistMode bist_ctrl Finish BistFail ErrMap Memory wrapper Q

96

SynTest Memory BIST Architecture

Memory Wrapper
Original From BIST Original From BIST Original Memory Control

Address

Data In

From BIST
BistMode
97

SynTest Memory BIST Architecture

Share BIST controller

BIST controller

wrapper0

wrapper1

mem_ctrl0 mem_ctrl bist_ctrl mem_ctrl1

98

SynTest Memory BIST Architecture

Group Memory

BIST controller

wrapper0

wrapper1

wrapper0

wrapper1

Group0 MemGroupSel[0] MemGroupSel[1:0]

Group1 MemGroupSel[1]

99

SynTest SRAMBIST Flow

100

SRAMBIST Flow
Study Spec.

Create Memory Description File

Create Test Algorithm No Generate BIST

Yes

Create BIST Configuration File

RTL Level Simulation

Synthesize the BIST RTL Code

Gate Level Simulation

101

Memory Spec. & MBIST Attribute

Study memory spec. form cell library document
Describe memory spec. in memory description file

(memory_name.mdf)

MBIST Attribute
Decide BIST clock rate Decide BIST clock trigger edge Do multiple memories share one bist controller?

Create Test Algorithm?

102

Memory Description File

BIST implement constraint BIST clock information

SRAM information I

BIST functional constraint

Cre ate TurboB IST_M e mory constraint file

SRAM information II

global information

other integration constraint

103

GLOBAL Section
%GLOBAL { %TIMESCALE 1ns/10ps; %SYNC_RESET TRUE; //Default: TRUE %CLK_CYCLE 20; //Same as memory //%BIST_CLK_TRIGGER posedge; %ANALYZER_ON_MEM TRUE; //Default: FALSE %RESET_PIN BIST_rst;//Default:Use BistMode }
Original Memory Port Memory Wrapper

Mux
BistMode

Memory

BIST Controller

mem_ctrl bist_ctrl Q

Analyzer

BistFail ErrorMap Finish

104

Memory Group Section

%MEMORY_GROUP { %GROUP c4mtram72x8,c4mtram72x8; %GROUP c4msram32x16s; }

105

Memory Section
%MEMORY c4msram32x16s { %TYPE SRAM; %DATA_BITS 16; %ADDR_BITS 5; %LOW_ADDR 5'b00000; %HIGH_ADDR 5'b11111; %LATENCY 0; %CLOCK CE; %SELECT -CSB; // %NO_MUX TRUE; %FORCE OEB = 0; %OTHER_INPUT PWN;

106

Memory Section
%MEMORY c4msrom0101 { %TYPE ROM;
%MISR_BITS 16; %MISR_POLY 15,3,1,0; %Q_CONNECT 15,13,12,11,0; %MISR_SEEDS 0000000111001010; %ROM_CONTENT_FILE rom.cod
rom.cod 110010 010110 111111 100000 .......

107

MISR
Polynomial:
cnXn+cn-1Xn-1+...+c1X+1

I0

I1

In-2

In-1

+ D1

+ D2

+ Dn-1

+ Dn

cn

cn-1

c2

c1

108

Port Section
%MEMORY c4msram32x16s { %PORT p1 { %TYPE %ADDRESS %DATA_IN %DATA_OUT %CLOCK %WRITE_EN %SELECT %OUTPUT_EN %READ_EN } %PORT p2

rw; A4,A3,A2,A1,A0; I; O; CE; -WEB; -CSB; -OEB; REN;

109

BIST Configuration File

%ALGORITHM MARCH_CM { %MARCH U{%W(0);} %MARCH U{%R(0);%W(1);} %MARCH U{%R(1);%W(0);} %MARCH D{%R(0);%W(1);} %MARCH D{%R(1);%W(0);} %MARCH D{%R(0);} %REPEAT_PAT 0 (0000,0011,0101); %REPEAT_PAT 1 (1111,1100,1010); }

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SRAMBIST
Command syntax:
srambist <options> <design name> srambist c4mtram72x8

Options
bcf_file <file name> algorithm <algorithm name> serial_test

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Input/Output Files
sram.mdf

sram_sim.v

srambist

sram.bist.rpt

sram_top.v sram_wrapper.v sram_rb.v

sram.scp sram.tcl

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RTL Level Simulation

sram_sim.v
sram.v sram_top.v sram_wrapper.v sram_rb.v

RTL level simulation

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Synthesis BIST RTL Circuit

sram_top.v sram_wrapper.v sram_rb.v sram.scp sram.tcl

synthesis tool

gate-netlist

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Reference
[1] J. Knaizuk, Jr. and C.R.P. Hartmann, An Optimal Algorithm for Testing Stuck-at-Faults in Random Access Memories, IEEE Trans. On Computers, 1977
[2] M.S. Abadir and J. K. Reghbati, Functional Testing of Semiconductor Random Access Memories ACM Computing Surveys 1983 [3] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Chichester, UK: John Wiley & Sons, Inc., 1991 [4]M. Marinescu, Simple and Efficient Algorithms for Functional RAM Testing, in Proc, of the International Test Conf. 1998
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