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M. R. Smith, Electrical and Computer Engineering, University of Calgary, Alberta, Canada smithmr @ ucalgary.ca
2000/03/05 1
To be tackled today
How RISCy Is DSP, IEEE Micro (Jan-10) Simply Signal Processing (Jan-40) Fast Scaling, CCI (Apr-10) Saturation Arithmetic (Apr-20)
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DSP Algorithms
When have you as a designer found a compromise that meets your requirements? As a consultant may have to add DSP characteristics to an existing system or add DSP coprocessor to an existing system
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
2000/03/05
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FIR
Multiply/Addition intensive Sum operation with high precision -- overflow considerations Long simple loop Online operation -- infinite amount of data Store coefficients on-chip for fast access Complex domain arithmetic
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IIR-1
Interrelated and order dependent multiplications and additions Small number of delays via register moves? short loop -- low number of instructions in loop which makes it difficult to optimize Precision -- very important because of feedback Multiple stages -- I.e. IIR follows IIR etc
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
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IIR-2 LDI
Short complicated loop Many intermediate values Pipeline issues because of interdependence
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FFT
Complex variables (A and B) and fixed coefficients (W) Address calculations complex Memory accesses numerable Multiplication and additions Need for fast access to many registers, address pointers, constants, variables
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
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DSP chips -- two cycle instructions (on top of FETCH/DECODE) during which the processor performs many parallel operations
Many processors takes 6 to 32 cycles to handle MULT, FMULT, FDIV or even FADD Make processor highly pipelined -- pipeline must be started and then kept full
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specialized decrement and branch instructions occurring in a single cycle instruction cached with counter superscalar operations delayed branches hardware loop control loop unrolling down counting loops
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
2000/03/05
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Harvard architecture branch target caches multi-ported memory register pre-forwarding -- avoid stalls while trying to write back result of ALU operation only to re-access the same register large register banks -- avoid memory ops associated with just calculated values
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
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FIR -- accumulated value can grow big IIR -- recursive use of a value External Memory bus width Internal Memory bus width Data width of registers and ALU Saturation arithmetic
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Saturation Arithmetic
For full discussion see 21K SHARC user manual and also Being Assertive with your processor (APR-20) Internal register 80 bits but external busses only 32 wide 0xFFFF F0000001 00000000
stored as F0000001 stored as 00000001 (normal math) stored as 80000000 (saturation) Can be good solution (FIR) or bad solution (IIR) to the problem of overflow
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
2000/03/05
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Need to fetch real and imaginary parts in at different times during the algorithm Need fast access to adjacent memory locations -- burst memory Need for many internal registers to temporarily store real/imaginary components (FFT butterfly and last years exams) Duplication of resources -- was custom, but consider now 21160
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
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DAG 1 8 x 4 x 32
BUS CONNECT
DMD BUS 64
DMD
REGISTER FILE 16 x 40
REGISTER FILE 16 x 40
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Complex addressing modes -- take many clock cycles Use pointers and autoincrement rather than calculating pointer + offset
need many address-related registers address calculations compete with ALU calculations group instructions within program
e.g. read and store often use same or similar addresses so dont recalculate the addresses.
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
2000/03/05
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standard memory access premodify postmodify circular buffers (modulo arithmetic on the address registers) bit-reverse addressing structure handling auto-increment with size accounted for
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
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Multi-processor operations
Application notes Good working environment Compatibility to previous processor versions -legacy code (advantage and a disadvantage)
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Get and then give instruction to multiplier Get and then give first, second data to multiplier Wait till cooked, and then get value
Newer chips have on-board multiplication or intelligent co-processors (F-LINE exceptions) Many chips do multiplication using specialized techniques introduced by optimizing compiler
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29K RISC FMULT execution takes 6 cycles + fetch 16bit x 16bit INTEGER multiplication on 68K CISC takes 70 cycles regardless of operations Use adds and shift instead since these take less time -- easy with integer, but floats?
What are equivalent operations on 21K. Discussed in early lecture on Quirks and SHARCs
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
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Multiplication by 2, 4, 8, 16
D2 = D0 * 19
MOVE.W D0, D2 ASL.W #4, D2 D2 = D0 * 16 ADD.W D0, D2 D2 = D0 * 17 ASL.W #1, D0 D0 = D0 *2 ADD.W D0, D2 D2 = D0 * 19 (29 cycles compared to 70) Watch out for overflow, may need conversion to 32 bits (SSI, SSF on some processssors -- not only 21k) Waste of time if have single cycle multipliers (21k?). Careful because multiplication results may end in special register.
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
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Need automated tools to schedule instructions Need multiple destinations (registers) for multiplier result Multiple and Accumulate (MAC) instruction Super-scalar operations even on a simpler processor Cause problems in short loops Many types of MACs needed
Not all processors have the 21061 single cycle multiplication operation
See In the AM29050 a FIR-bearing animal (FEB-80 in ENCM515 -- Characteristics needed in DSP processors 2000/03/05class notes)) 22 / 48 Copyright smithmr@ucalgary.ca
N point DFT
; 0 <= n < N
result = 0; do { Numerator = Numerator - Denom; result++; } while (Numerator > 0); result--;
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Division by 2, 4, 8, 16
The FDIV on 29K takes 15 cycles There is not a FDIV on the 21K -- use recursion!!
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31.98125 1023.4
0x41 FF D9 9A 0x44 7F D9 9A
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Fast scaling Routine for Floating-point RISC and DSP processors (APR-10) Floating Point Format
31 S
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23 22 bexp frac
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
0
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3 (0x1.4 x 2 )
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31.98125 1023.4
1.frac
0x41 FF D9 9A 0x44 7F D9 9A
0 0
0x83 0x88
0x7F D9 9A 0x7F D9 9A
Remember JAMES BOND helped by M (Smith) The ONE is remembered and not stored
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1.0 32.0
31.98125 1023.4
0 0
0 0
0x7F 0x00 00 00 0x84 0x00 00 00 BEXP DIFF = 5 0x83 0x7F D9 9A 0x88 0x7F D9 9A BEXP DIFF = 5
K = K / -1
-- flip the sign bit with XOR instruction p K = K / N where N = 2 -- decrease bexp = bexp -5
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F0 = 1.0 R0 = R8 - R0
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PROBLEMS?
Must be overcome on many processors Non-issue on 21k which has single cycle multiplication and division. Calculate reciprocal and then multiply
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
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ADD.W R0, R1
Every addition (subtraction) result has the possibility of being out of range -- overflow. Must be tested. 68K solution
ADD.W R0, R1 BVS Somewhere <- Test takes cycles
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Specialized coding techniques e.g. 29k has the ability of throwing SWI as part of compare (ASSERT) Test for FP number too small from previous special Division operation
CMP.L #toosmall, D0 BGE okay MOVE.L #0, D0 BRA continue okay: SUB.L #b_exp, D0 continue: 68K code <- EXTRA cycles always executed
ASGE TRAP#, temp, BEXPchange <- Only compare for 29k SUB gr96, gr96, BEXPchange <- Not in a delay slot? where TOOSMALL: CONST gr96, 0 RTI
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R0 = 5
R0 = ASHIFT R0 BY 23 F1 = minimum value ( 2^(5-127) ) F2 = ABS F4 COMP (F2, F1) IF GE R4 = R4 - R0 ELSE R4 = R4 - R4 <- NO DELAY
Cant use
ELSE R4 = 0
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This is not a legal instruction either!! COMPUTE instructions take 22 bits to describe IF JUMP/CALL ELSE R4 = R4 - R4 is allowed
Useless approach anyway since there are better ways on 21k to do repeated division by a constant.
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
2000/03/05
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Processors compared
RISC
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Harvard architecture MAC (rather than Super -- Scalar instructions) Ability to do X = R+S, Y = R-S operations many registers for address/values FP as well as integer capability Bit-reverse addressing Peripherals with DMA Low power standby High precision -- double precision Efficient pipeline with parallel completion of many operations (dual-ported memory and register banks)
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
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Comparisons -- 1
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FIR/IIR
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Fast instruction cycle -- different from high clock speed Cycle time adjustable according to instruction type Fast hardware multiplier Floating point for easier algorithm design High precision, implying wide data buses for memory, internal processor transfers, registers and on-board processing units
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Several data buses available to reduce bus conflict transfer overhead Harvard architecture and/or instruction cache to avoid instruction and data-fetch clashes Duplicate resources for parallel computation of real and imaginary components of complex numbers Dedicated hardware required for address calculations to avoid APU clash with main algorithm
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Fast and reliable, easily programmed, developed and upgraded Inexpensive and easy to develop peripherals High level of customer support Inexpensive to purchase Lower power consumption with a standby mode
ENCM515 -- Characteristics needed in DSP processors Copyright smithmr@ucalgary.ca
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Several data buses available to reduce bus conflict transfer overhead Harvard architecture and/or instruction cache to avoid instruction and data-fetch clashes Duplicate resources for parallel computation of real and imaginary components of complex numbers Dedicated hardware required for address calculations to avoid APU
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Tackled today
How RISCy Is DSP, IEEE Micro (Jan-10) Simply Signal Processing (Jan-40) Fast Scaling, CCI (Apr-10) Saturation Arithmetic (Apr-20)
2000/03/05
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