S.O.I.

(SILICON ON INSULATOR)

PRESENTED BY:

ARUN KUMAR PANDEY PREETAM KUMAR

CONTENTS
INTRODUCTION WHAT IS SOI ? WHY SILICON ON INSULATORS ? FABRICATION OF SOI MECHANISM OF SOI TYPES OF SOI FDSOI PDSOI FDSOI v/s PDSOI EXPERIMENTS WITH SOI ADVANTAGES OF SOI TECHNOLOGY DISADVANTAGES OF SOI TECHNOLOGY APPLICATION OF SIO TECHNOLOGY SOI -POWER DISSIPATION SCALING & COST INDUSTRIAL NEEDS USE IN MICROELECTRONICS INDUSTRY SOI CHIP v/s CMOS CHIP CONCLUSION AND FUTURE WORK REFERENCES

INTRODUCTION:
Latest fabrication technology.

Chip in a Blanket. Silicon-on-Silicon. Increasing demand for high performance, low power & low area among micro-electronic device led to its invention.

INVENTION:
SOI (silicon-on-insulator) has been known for ~ 20 years. In 1993 Honeywell started product development of SOI to support commercial aircraft electronic engine controls. First it was used for military purposes in U.S.A.

What is

S.O.I. ?
It is the latest fabrication technique. It is easier & cheaper. Transistors are build on a silicon layer resting on insulating layer of silicon-di-oxide known as BOX (burried oxide). Only a thin layer from a face of the wafer used for making electronic components, the rest essentially serves as mechanical support.

WHY S.O.I.
Higher speed. Less power consumption. Easier fabrication. Cheaper etching process.

To enhance the performance.

More electronic devices can be fabricated on

same chip (30% more than bulk). It reduces parasitic capacitance when compared to bulk or epi-wafers.

FABRICATION OF S.O.I. ?
Fewer mask and ion implementation steps (because of the elimination of well & field isolation implements). Less complex (costly) lithography and etching required to achieve next-generation performance.

Some fabrication process:

SIMOX Separation by Implantation of Oxygen Smart-cut SOI Technology BESOI Bond and Etch-back SOI SOS Silicon-on-Sapphire

SIMOX(Separation by Implantation of Oxygen):

High temperature Annealing process is used. Right dose of oxygen is implemented on Si to form SiO2. Ion Impementation technique (Ion of a material are accelerated in an electric field and impact into the other solid is called Ion Impementation technique) is used.

Smart-cut SOI Technology:

The Smart Cut process was developed and is patented by SOITEC corporation from France. Technological Process that enables the transfer of very fine layers of crystalline material onto a Mechanical Support.

BESOI (Bond and Etch-back SOI):

It is the technique of fabrication of semiconductor device or interconnection of electronic device to form desired circuit. It is done after formation of SOI wafer.

SOS (Silicon-on-Sapphire):
It is a part of SOI family of CMOS technique. In this process layer of silicon is grown on sapphire (Al2O3). It is a hetero-epitaxial process

HOW IT IS...
FASTER (20% to 35% than BULK)? CONSUME LESS POWER (35% to 70% then BULK)? DENSER FABRICATION (due to better isolation property)? CHEAPER FABRICATION METHOD (due to cheaper etching process)?

BULK

S.O.I.

1. Charge collection decreases significantly in SOI device.

BULK

2. Low junction capacitance (Hence less power dissipation).

TSOI

BULK

S.O.I.

3. Better isolation lets denser fabrication: It is recognized by

IBM that 30% more electronic devices than those of bulk can be fabricated in SOI.

4. Latch up Elimination: SOI has no wells into the substrate and

therefore no latch up or leakage path.
P+ N+ N+ P+ P+

P-well N-Substrate
A: Cross-section of bulk CMOS inverter

N+ P+ N+

P+ P

P+

Buried oxide Si-substrate

B: Cross-section of a SOI CMOS inverter

5. Self heating:
SOI wafer creates a potential temperature delta between device called local heating or self heating. This happens only when there is logic switching in the device. It has less impact on digital circuit but huge impact on analog circuit.

6. False switching:
A low gain parasitic bipolar transistor on every floating body SOI FET transistors. Bipolar transistor is in parallel with the FET transistor and can cause false switching to the off FET transistor. Over the years of the technology scaling, this bipolar current effect has been pretty much eliminated due to the reduction of the operating voltage of the 90nm node and beyond.

S.O.I. v/s BULK

SOI device delay SOI Power dissipation

SOI results in at least 30% lower delay compared to bulk.

Scaling with SOI

SOI results in about 70% lower power for the same speed.

TYPES OF S.O.I.:

SOI
PD-SOI
(Partially DepletedSOI)

FD-SOI (Fully
Depleted-SOI)

1. Partially Depleted SOI(PD-SOI):

Silicon dioxide layer is thicker History dependent The exact voltage depends on the history of source, gate, and drain voltages leading up to the current time (the history effect).
TSOI WT , where WT 2 s (2F ) qNbody
Where, Tsoi = thickness of insulator Wt= width of substrate

2. Planer Fully Depleted SOI:

FD-SOI technology relies on an ultrathin layer of silicon over a Buried Oxide (commonly called BOX). History independent
T W , where W 2 s (2F ) SOI T T qNbody Source
Where, Tsoi = thickness of insulator Wt= width of substrate

Gate SOI SiO2 Silicon Substrate Drain

Floating body effect:

Usually seen in Partially-Depleted S.O.I. As shown in figure, the MOS structure is accompanied by a parasitic bipolar device in parallel. The base of this device is floating.

History Effect In PDSOI:

1. In PDSOI the next switching Input time marginally depends on previous switching time 2. The second switch is seen to be faster than the first switch Output
This is known as History

Effect.

First switch

Second switch

Fig.: Differentiating BULK Devices from PD-SOI & FD-SOI:

Experiments with S.O.I.:

Characteristics of defects created on silicon on insulator (SOI) wafers by each of various contaminants, specifically iron, nickel, and molybdenum.

Results: Iron

Small amount of tiny pits are seen

Results: Nickel Smaller amount of tiny pits are seen

Result: Molybdenum
No or negligible tiny pits are seen

ADVANTAGES Of
Suitable for high-energy radiation environments.

S.O.I. :

Parasitic capacitances of SOI devices are much smaller.

No latch-up.

ADVANTAGES (contd..):
Elemination of Substrate Noise

Less Temperature Sensitivity

ADVANTAGES (contd..):
Easier device isolation. High device density. Easier scale-down of threshold voltage.

SOI technology is useful for implementing high-speed op-amps given its low Voltage.
Higher transconductance (especially of FD) implies higher gain. Lower power consumption compared to bulk devices at low current level.

ADVANTAGES (contd..):
Uses in digital and analog circuits A combination of FD and PD devices are used in digital circuitry. Used for making SIO CHIPS Superior capabilities of SOI CMOS technology usage in memory cell implementation.

LIMITATIONS OF

S.O.I.

Major bottleneck is high manufacturing costs of the wafer. Floating-body effects impede extensive usage of SOI.

Floating body causes the History Effect Self-heating

APPLICATIONs
.Daily

use product such as markets such as : Mobile Internet Devices (Smartphones, Tablets, Netbooks ), Imaging (Digital Camera, Camcorders), Cellular Telecom, Mobile Multimedia, Home Multimedia (Set Top Box, TV, Blu-Ray), Automotive Infotainment, etc.

Digital Camera

Broadband Modems

Applications according to thickness :

SOI Wafer Classificatio n on (BOX)
Ultra-thin Ultra-thin Thin

BOX System Level IC Type Thickness, in Application Microns

< 0.15 < 0.15 0.15 to 1 High End PCs Servers Workstation MPU MPU ASIC Logic

Key System Requirement

High Speed High Speed High Speed/Small Die Low Voltage/Power High Speed Low Voltage/Power High Power Low Voltage/Power Radiation Hardened High Power

Thin Thin Thin Thin Thin Thick Thick

0.15 to 1 0.15 to 1 0.15 to 1 0.15 to 1 0.15 to 1 0.5 to 5 0.5 to 5

Handsets/PDA Mainframes Portable Wireless Automotive Consumer Digital Military/Aeros pace Industrial

Mixed Signal High End Logic RF/IF trans/rec Mixed Signal ASIC Logic RF/IF trans/rec Bipolar, Power ICs

Conclusion AND FUTURE WORK:

We have investigated the SOI technology and its application to next generation low power, high performance DRAM systems by intensive simulations.

Our experimental results show that SOI can reduce the Cb/Cs ratio significantly which implies either further Cs reduction or lower operation voltage.
Due to its characteristics, SOI is fast becoming a standard in IC fabrication. Several companies have taken up SOI manufacturing. High-volume production of SOI is yet to become common.

References:
J.P. Colinge, Silicon-On-Insulator Technology: Materials to VLSI, Second Edition

D. K. Sadana and M. Current, Fabrication of SiliconOn-Insulator (SOI) Wafers Using Ion Implantation. J. Kuo, Low- Voltage SOI CMOS VLSI Devices and Circuits. http://www.seminarprojects.com http://en.wikipedia.org/wiki/silicononinsulator http://www.jpl.nasa.gov http://www.google.com