COE 381 MICROPROCESSORS

UNIT 3 MICROPROCESSOR INTERFACING

Chapter Objectives
I/O Addressing Compromises / Extensions Types of Bus-based I/O

Microprocessor Interfacing: Interrupts Multilevel Bus Architectures

Direct Memory Access

Arbitration

Error Detection and Correction

SECTION 1:

MICROPROCESSOR INTERFACING

Embedded System
Embedded system has three functionality aspects: Processing
Transformation of data Implemented using processors

Storage
Retention of data Implemented using memory

Communication
Transfer of data between processors and memories Implemented using buses Called interfacing

Embedded System
CPU MEM

I/O

Simple Bus
Wires are conducting channels interconnecting system devices and components
may be uni-directional or bi-directional

Bus is a set of wires with a single function e.g. address bus, data bus
Though may also be an entire collection of wires with various functionalities

Protocol is a set of rules for communication over the wires or a bus

Bus Structure
rd'/wr enable

Processor

addr[0-11]

Memory

data[0-7]

bus

bus structure

Ports
A port is a conducting device on periphery of a design entity
e.g. a port connects a bus to processor or memory

Ports are often referred to as pins Actual pins are located on the periphery of an IC package and plugs into a socket on a pc board. Sometimes metallic balls are used instead of pins A pad may be a single wire or set of wires with single function within a chip
e.g., 12-wire address port

Ports
rd'/wr Processor Memory

port

enable

addr[0-11]

data[0-7]

bus

Timing Diagrams
Most common method for describing a communication protocol is by the use of timing diagrams On a timing diagram, time proceeds to the right on x-axis A control signal may be low or high at some intervals
1

assert is used to indicate that the signal is made active and deassert means deactivated Asserting go means set go=0
Invalid

Data signal may be valid or not

valid

Timing Diagrams
A bus protocol may have sub-protocols A sub-protocol is also called a bus cycle
e.g., read and write

Each bus cycle may take several clock cycles

Read Protocol
rd'/wr
0

enable
addr

data
tsetup tread

read protocol

Write Protocol
rd'/wr enable addr data tsetup twrite

write protocol

Basic Protocol Concepts

Actor: design entity (e.g. processor or memory) involved in the data transfer
May master, slave or peer

Direction: sender, receiver Addresses: special kind of data that specifies a location Time (division) multiplexing: Sharing a single set of wires for multiple pieces of data
save amount of wires at expense of time

Time-Multiplexing
Time-multiplexed data transfer
Send 16 bit data over 8 bit databus Master data(15:0) mux data(8) req Servant data(15:0 ) demux Master addr dat a mux addr/data req Servant addr dat a demux Send both data and address through a single bus

req data 15:8 7:0

req addr/data addr data

data serializing

address/data muxing

Control Methods
Master req Servant

Master

req ack

Servant

data
req data 1 2 taccess
Master wants to receive data 1. Master asserts req (uest) to receive data 2. Servant puts data on bus within time taccess 3. Master receives data and deasserts req 4. Servant ready for next request Strobe protocol (faster if response time of servant is known)

data
3 4 req ack data
Master wants to receive data 1. Master asserts req to receive data 2. Servant puts data on bus and asserts ack to indicate data is ready and valid 3. Master receives data and deasserts req 4. Servant ready for next request Handshake protocol (better if there are multiple servants with different response times ack line required)

1 2

3 4

A Strobe/Handshake Compromise
Master req wait data Servant

req
wait data

1
2

3
4

req 1
wait data 2 3

4
5

taccess 1. Master asserts req to receive data 2. Servant puts data on bus within time taccess (wait line is unused) 3. Master receives data and deasserts req 4. Servant ready for next request Fast-response case

taccess 1. Master asserts req to receive data 2. Servant can't put data within taccess, asserts wait 3. Servant puts data on bus and deasserts wait 4. Master receives data and deasserts req 5. Servant ready for next request Slow-response case

I/O Addressing
A microprocessor communicates with other devices using some of its pins (non-control pins)
For an I/O device, communication may be port-based or bus-based

Port-based I/O (parallel I/O) the processor has one or more Nbit ports, connected to dedicated registers
e.g., P0 = 0xFF; v = P1; where P0 and P1 are 8-bit ports

For bus-based I/O the processor has address, data and control ports that form a single bus Communication protocol is built into the processor
a single instruction carries out Read (or Write) sub-protocol on the bus

Compromises/Extensions
Parallel I/O peripheral:
When processor only supports busbased I/O but parallel I/O needed

Extended parallel I/O:

When processor supports port-based I/O but more ports needed

Compromises/Extensions
Processor Memory System bus Address, system and control lines Parallel I/O peripheral Processor Port 0 Port 1 Port 2 Port 3 Parallel I/O peripheral

Port A

Port B

Port C

Port A

Port B

Port C

Adding parallel I/O to a bus-based I/O processor

Extended parallel I/O

Types of Bus-based I/O

Processor talks to both memory and peripherals using same bus in two ways
memory-mapped I/O
address space is divided between memory and I/O

Standard I/O
entire address space is available for memory access entire address space is available for I/O access required accessmemory or I/O? Need to indicate.

Memory-Mapped I/O vs. Standard I/O

Merits of memory-mapped I/O no requirement for special instructions for I/O access instructions involving memory also work with peripherals Standard I/O requires special instructions to move data from/to peripheral registers Merits of standard I/O no partial loss of memory address space to peripherals simpler address decoding logic in peripherals is possible

Microprocessor Interfacing
Polling
Processor polls peripherals regularly Wasteful if too frequent Ineffective if not frequent enough

Interrupt-driven
Peripheral interrupts processor when servicing is required Upon interrupt assertion
Processor suspends current task Jumps to and run the appropriate ISR in response Interrupt detection mechanism implemented in hardware

Extra pin(s) to facilitate interrupt reception

Interrupts
Fixed interrupt
An address is built into processor Either ISR starts from the address or a jump-to-ISR instruction is stored there To service multiple peripherals several interrupt pins needed

Vectored interrupt
Peripherals provide addresses of their associated ISRs Commonly used when multiple peripherals are connected by system bus Only one interrupt pin necessary

Compromise: interrupt address table of known location, peripherals provide indices into table

Example: Interrupt in Action

Processor running main program: currently executing instruction from location 100 Peripheral 1 (a sensor) sends an interrupt ISR reads data from sensor, then transform and write it to Peripheral 2 (a display)

Interrupt with Fixed ISR

The Case of Vectored Interrupt

Vectored Interrupt (2)

Program memory ISR 16: MOV R0, 0x8000 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return ... Int Main program ... 100: instruction 101: instruction 100 Inta Int PC 1 P1 16 P2 P Data memory

System bus

0x8000

0x8001

Vectored Interrupt (3)

3: After completing instruction at 100, P sees Int asserted, saves the PCs value of 100, and asserts Inta
Program memory ISR 16: MOV R0, 0x8000 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return ... Main program ... instruction 101: instruction
100 1

Data memory

Inta Int PC

P1 16 0x8000

P2

0x8001

Vectored Interrupt (4)

4: P1 detects Inta and puts interrupt address vector 16 on the data bus
Program memory ISR 16: MOV R0, 0x8000 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return ... Main program ... instruction 101: instruction 100 Inta Int PC P Data memory

P1
16 16 0x8000

P2

0x8001

Vectored Interrupt (5)

5(a): PC jumps to the address on the bus (16). The ISR there reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001. 5(b): After being read, P1 deasserts Int.
Program memory ISR 16: MOV R0, 0x8000 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return ... Main program ... 100: instruction 101: instruction 100 System bus P Data memory

Inta Int PC
0

P1
16 0x8000

P2

0x8001

Vectored Interrupt (6)

6: The ISR returns, thus restoring the PC to 100+1=101, where the P resumes
Program memory ISR 16: MOV R0, 0x8000 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return ... Main program ... instruction 101: instruction 100 System bus P Data memory

Int PC
+1

P1 0x8000

P2 0x8001

Interrupt Address Table

A compromise between fixed and vectored interrupts A table in memory holds ISR addresses
maybe 256 words

A peripheral provides just an index into the table

fewer bits sent by the peripheral

ISR location can be moved without changing peripheral Only one interrupt pin required

Maskable and Non-Maskable Interrupts

A maskable interrupt
A programmer can set a bit (or bits) to cause processor to ignore the interrupt Important when processor is responding to critical situations

A non-maskable interrupt
A separate interrupt pin that cannot be masked Reserved for drastic situations

Direct Memory Access (DMA)

More efficient in buffering peripheral data in memory DMA controller is a single purpose processor
moving data between peripherals and memory

DMA (2)
Peripheral makes a request to DMA to write data to the memory DMA requests system bus control from the P P relinquishes control of bus to DMA controller
no jumping into an ISR with its attendant overhead

Regular program need not wait

unless it requires the system bus

In the case of Harvard architecture:

processor can fetch and execute instructions, but no access to data memory

Direct Memory Access (DMA)

Three main steps are involved in DMA
Processor sets up DMA by supplying 1) device identity, 2) operation to perform, 3) Source or destination memory address, and 4) number of bytes to transfer
DMA starts and DMA controller arbitrates for the bus DMA transfer completes DMA controller interrupts CPU, and CPU checks for any possible errors

Direct Memory Access (DMA)

Overhead of DMA I/O Systems
For previous hard disk systems assume initial setup for DMA takes 1000 clock cycles, handling interrupt at DMA completion takes 500 cycles, and average transfer from disk is 8 kB
Average fraction of CPU time consumed is 0.15%

Intel 8237 DMA Controller

D[7..0] A[19..0] ALE MEMR MEMW IOR IOW HLDA HRQ
Intel 8237 REQ 0 ACK 0 REQ 1 ACK 1 REQ 2 ACK 2 REQ 3 ACK 3

Transfer Without DMA

Recall example on vectored interrupt

Transfer With DMA

1(a): P is executing its main program. It has already configured the DMA ctrl registers. 4: After executing instruction 100, P sees Dreq asserted, releases the system bus, asserts Dack, and resumes execution. P stalls only if it needs the system bus to continue executing. 3: DMA ctrl asserts Dreq to request control of system bus. 5: (a) DMA ctrl asserts ack (b) reads data from 0x8000 and (b) writes that data to 0x0001. 1(b): P1 receives input data in a register with address 0x8000. Time

2: P1 asserts req to request servicing by DMA ctrl.

7(a): P de-asserts Dack and resumes control of the bus.

6:. DMA de-asserts Dreq and ack completing handshake with P1.

7(b): P1 de-asserts req.

Transfer With DMA

Program memory P 0x0000

Data memory 0x0001

No ISR needed!

System bus

... Main program ... 100: instruction 101: instruction PC

Dack Dreq

DMA ctrl 0x0001 0x8000 ack

P1

req

0x8000

100

Transfer With DMA

Program memory No ISR needed! System bus P 0x0000 Data memory 0x0001

... Main program ...

100: instruction 101: instruction PC 100

Dack Dreq 1

DMA ctrl 0x0001 ack req 1

P1

0x8000

0x8000

Transfer With DMA

Program memory No ISR needed!

P
0x0000

Data memory 0x0001

System bus
1

... Main program ... 100: instruction 101: instruction PC 100

Dack Dreq

DMA ctrl

P1

0x0001
0x8000

ack req 0x8000

Transfer With DMA

Program memory P 0x0000 Data memory 0x0001 No ISR needed! System bus

... Main program ... 100: instruction 101: instruction PC 100

Dack Dreq

DMA ctrl 0x0001 0x8000 ack req

P1

0x8000

Transfer With DMA

Program memory P 0x0000 Data memory 0x0001 No ISR needed! System bus

... Main program ... 100: instruction 101: instruction

Dack Dreq 0

DMA ctrl

0x0001
0x8000

ack req

P1

PC
100

0x8000

Priority Arbiter
Multiple peripherals request service from single resource (e.g., microprocessor, DMA controller) simultaneously Which one gets serviced first? A priority arbiter provides a solution
A single-purpose processor is the arbiter makes requests to the resource on behalf of the requesting peripheral with the highest priority

The arbiter is connected to system bus for the purpose of configuration only

Priority Arbiter (2)

Microprocessor System bus Inta Int 3 Ireq1 Iack1 Ireq2 Iack2 6 5 Priority arbiter Peripheral1 2 Peripheral2 2 7

Types of Priority
There are two types of priority Fixed priority
each peripheral has unique rank highest rank is chosen first in the event of simultaneous multiple requests preferred when a clear difference in rank between peripherals exists

Rotating priority (or round-robin)

priority changes based on history of servicing This affords better distribution of servicing Used especially among peripherals with similar priority demands

Intel 8259 Programmable Priority Controller

D[7..0] A[0..0] RD WR INT INTA Intel 8259 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

CAS[2..0] SP/EN

Daisy-chain Arbitration
Arbitration by peripherals themselves Arbitration functionality built into the peripheral or provided by added external logic req input and ack output on peripherals Peripherals connected together in a daisy-chain manner

Priority Arbiter
P System bus

Peripheral1 Inta Int Ack_in Ack_out Req_ou Req_in t

Peripheral2 Ack_in Ack_out Req_out Req_in 0

Daisy-chain aware peripherals

Pros and Cons of Daisy-chain

Easy to add/remove peripheral - no system redesign needed Does not support rotating priority One broken peripheral can cause loss of access to other peripherals

Network-oriented Arbitration
When multiple microprocessors share a bus (sometimes called a network) Arbitration typically built into bus protocol
Separate processors may try to write simultaneously causing collisions

This arbitration is typically used for connecting multiple distant chips

Multilevel Bus Architectures

Using one bus for all communication
Requires high-speed, processor-specific bus interface Excess gates, power consumption, and cost System less portable Many peripherals can lead to slow-down of bus

Multilevel bus architecture

When one-bus-for-all-communication is not desirable

Multilevel Bus Architectures (2)

Microprocessor Cache Memory controller DMA controller

Processor-local bus Peripheral Peripheral Peripheral Bridge

Peripheral bus

Advanced Communication Principles

Layering
breaking complexity of communication protocol into pieces

Pieces are called layers of the protocol

Easier to design and understand Lower layers provide services to higher ones Higher level might work with packets of data

Advanced Communication Principles (2)

Parallel communication:
Physical layer capable of transporting multiple bits of data at a time

Serial communication
Physical layer transports one bit of data at a time

Wireless communication
No physical connection needed for transport at physical layer

Parallel Communication
Multiple data, control, and possibly power wires are involved A word is sent one bit per wire High data throughput

Used over short distances

Serial Communication
Serial: bits sent in sequence one at a time higher data throughput over long distances due to low average capacitance Cheaper and less bulky

Serial Communication (2)

more complex interfacing logic and communication protocol
Sender needs to decompose word into bits Receiver needs to recompose bits into word Control signals often sent on same wire as data

Serial Communication (3)

Often more complex electrical connections than just one wire
Fibre-Optic
Uses light to communicate

Low Voltage Differential Signal (LVDS)

Consists of two signals: one is the inversion of the other

Wireless Communication
Infrared (IR)

Electromagnetic wave just below visible light spectrum Diode emits infrared light to generate signal Infrared transistor detects signal Cheap to build Line-of-sight, limited range
Electromagnetic wave in radio spectrum Analog circuitry and antenna on both sides of T-mission Line of sight is not needed Range is determined by transmitter power

Radio frequency

Error Detection and Correction

Often part of bus protocol Error detection
ability of receiver to detect errors during transmission

Error correction
ability of receiver and transmitter to cooperate to correct errors
Typically done by acknowledgement/retransmission protocol

Error Detection and Correction (2)

Bit error: single bit is inverted Burst of bit error: consecutive bits received incorrectly Parity: extra bit sent with word used for error detection Checksum: extra word sent with data packet of multiple words