Syllabus

UNIT V SPECIFICATION USING VERILOG HDL 9 Basic Concepts: Identifiers - gate primitives, gate delays, operators, timing controls, procedural assignments, conditional statements. Coding Methods: Data flow and RTL, structural, gate level, switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches. Examples: Structural gate level description of decoder, equality detector, comparator, priority encoder, half adder, full adder, Ripple carry adder, D latch and D flip flop.

Unit II - Lesson Plan

Lecture No. 1 2 3 4 5 6 7 Topics to be covered
Introduction, basic concepts- Identifiers- Gate primitives Data flow, Structural, Behavioural Modeling Gate delays, Operators Half adder, Full adder, Ripple carry adder Timing controls, Procedural assignments Decoder, Equality detector, Comparator Priority encoder, D latch and D flip flop.

8 9

Conditional statements
Test benches

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BASIC CONCEPTS - VerilogHDL: VerilogHDL is a hardware-description-language (HDL) that can be used to model a digital system (circuit). The VerilogHDL language has capabilities to describe the behavioral nature of a design, the dataflow nature of a design, a design's structural composition. A design can be modeled in three different styles or in a mixed style. These styles are: 1. Behavioural style - modeled using procedural constructs; 2. Dataflow style - modeled using continuous assignments; 3. Structural style - modeled using gate and module instantiations. Primitive logic gates, such as and, or and nand, are built-in into the language. Switch-level modeling primitive gates, such as pMOS and nMOS, are also built-in into the language. There are two data types in VerilogHDL; the net data type and the register data type. Hierarchical designs can be described, up to any level, using the module instantiation construct.

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Verilog HDL can be used to perform response monitoring of the design under test, that is, the values of a design under test can be monitored and displayed. These values can also be compared with expected values, and in case of a mismatch, a report message can be printed. In addition, the language provides a programming language interface through which the internals of a design can be accessed during simulation including the control of a simulation run. The Programming Language Interface (PLI) is a powerful feature that allows the user to write custom C code to interact with the internal data structures of Verilog. The language inherit, many of its operator symbols and constructs, from the C programming language. A design can be of arbitrary size; the language does not impose a limit. Verilog HDL is non-proprietary and is an IEEE standard.

Module The basic unit of description in Verilog is the module. A module describes the functionality or structure of a design and also describes the ports through which it communicates externally with other modules. Here is the basic syntax of a module. module module_name (port_list) ; Declarations: reg, wire, parameter, input, output, inout, function, task, . . . Statements: initial statement always statement Module instantiation Gate instantiation Continuous assignment endmodule

Declarations are used to define the various items, such as registers and parameters, used within the module.
Statements are used to define the functionality or structure of the design. Declarations and statements can be anywhere within a module; however, a declaration must appear before its use. For clarity and readability it is best to put all declarations before any statements.

Data Flow Modeling (Boolean expression) 1. The basic mechanism used to model a design in the Dataflow style is the continuous assignment. 2. In a continuous assignment, a value is assigned to a net. The syntax of a continuous assignment is: assign [delay] LHS_net = RHS_expression; e.g., assign #3 Z[0] = (Abar & Bbar & EN); 3. The delay specifies the time duration between a change of operand on the righthand side and the assignment to the left-hand side. If no delay value is specified, the default is zero delay. module mux4_to_1 (out, i0, i1, i2, i3, s1, s0); output out; input i0, i1, i2, i3; input s1, s0; //logic equation for out assign #5 out = (~s1 & ~s0 & i0) | (~s1 & s0 & i1)|(s1 & ~s0 & i2)|(s1 & s0 & i3); endmodule

Comments There are two forms of comments in Verilog HDL. 1. /* First form: Can extend across many lines */ 2. / / Second form: Ends at the end of this line. Format Verilog HDL is case-sensitive. That is, identifiers differing only in their case are distinct. In addition, Verilog HDL is free-format, i.e., constructs may be written across multiple lines, or on one line. White space (new line, tab, and space characters) have no special significance. Here is an examplethat illustrates this. initial begin Top = 3' b001; #2 Top = 3' b011; end is same as: initial begin Top =3 b001; #2 Top = 3b011; End

Identifiers: 1. Identifiers are names given to objects, so that they can be referenced in the design. 2. Identifiers are made up of alphanumeric characters, the underscore ( _ ), or the dollar sign( $ ). 3. Identifiers are case sensitive. Identifiers start with an alphabetic character or an underscore. They cannot start with a digit or a $ sign. Here are some examples of identifiers. 1. Count COUNT (Distinct from Count) 2. _R2_D2 R56_68 FIVE$ Escaped identifiers begin with the backslash ( \ ) character and end with whitespace (space, tab, or newline). All characters between backslash and whitespace are processed literally. Any printable ASCII character can be included in escaped identifiers. e.g., \a+b-c , \**my_name** Verilog HDL defines a list of reserved identifiers, called keywords, that can only be used in certain contexts. Only the lower case keywords are reserved words.

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Describing in Structural Style (Gate level (or structural)Modeling) Structure can be described in VerilogHDL using: i. Built-in gate primitives ii. Switch-level primitives iii. User-defined primitives iv. Module instances (to create hierarchy) Interconnections are specified by using nets. 'timescale 1ns / 1ns module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
//port declaration from the I/O diagram.

// port list is taken from the I/O diagram.

output out; input i0, i1, i2, i3; input s1, s0;
// Internal wire declarations

wire s1n, s0n; wire y0, y1, y2, y3;

// Gate instantiations

not N1 (s1n, s1); not N2 (s0n, s0); and A1 (y0, i0, s1n, s0n); and A2 (y1, i1, s1n, s0); and A3 (y2, i2, s1, s0n); and A4 (y3, i3, s1, s0); or O1 (out, y0, y1, y2, y3); endmodule

// create s1n and s0n signals. // 3-input and gates instantiation

// 4-input or gate instantiation

Describing in Behavioral (Algorithmic-level) Style 1. The behavior of a design is described using procedural constructs. These are: 2. (i) Initial statement: This statement executes only once. 3. (ii) Always statement: This statement always executes in a loop, that is, the statement is executed repeatedly. 4. Only a register data type can be assigned a value in either of these statements. 5. Such a data type retains its value until a new value is assigned. All initial statements and always statements begin execution at time 0 concurrently.

Describing in Behavioral (Algorithmic-level) Style module mux4_to_1 (out, i0, i1, i2, i3, s1, s0); output out; input i0, i1, i2, i3; input s1, s0;
// output declared as register

reg out;
// recomputed the signal out, if any input signal changes. // all input signals that cause a recomputation of out to occur must go into the // always@ () sensitivity list.

always @ (s1 or s0 or i0 or i1 or i2 or i3) begin case({s1, s0}) 2b00 : out = i0; 2b01 : out = i1; 2b10 : out = i2; 2b11 : out = i3; endcase end endmodule

Built-in Primitive Gates (Gate Primitives) The following built-in primitive gates are available in Verilog HDL.
1. 2. 3. 4. 5. 6. Multiple-input gates: and, nand, or, nor, xor, xnor. Multiple-output gates: buf, not. Tristate gates: bufif0, buffif1, notif0, notif1. Pull gates: pullup, pulldown. MOS switches: cmos, nmos, pmos, rcmos, rnmos, rpmos. Bidirectional switches: tran, tranif0, tranif1,rtran, rtranif0, rtranif1.

A gate can be used in a design using a gate instantiation. Here is a simple format of a gate instantiation. gate_type [ instance_name] ( terml , term2 , . . . , termN) ; e.g., nand N1 (out1, in1, in2, in3); e.g., not INV (Abar, A); ----------------------------------------------------------------------------------------------------module halfadd (A,B, sum,carry);
input A, B; output sum, carry; and a1 (carry, A,B); xor x1 (sum, A, B);

endmodule

Data types: Verilog HDL has two groups of data types. (i) Net type. (ii) Register type. 1. Net type :It represents a physical connection between structural elements. Its value is determined from the continuous assignment or a gate output. 2. Register type: It is assigned values only within an always statement or an initial statement. Value Set: Verilog HDL has the following four basic values. i. 0 : logic-0 or false ii. 1: logic-1 or true iii. x : unknown iv. z: high-impedance Vectors (multiple-bit) Nets or reg data types can be declared as vectors (multiple bit widths). If bit width is not specified, the default is scalar (1-bit). i. wire a; // scalar net variable, default ii. wire [7:0] bus; // 8-bit bus iii. wire [31:0] busA, busB, busC; // 3 buses of 32-bit width. Vectors can be declared at [high# : low#] or [low# : high#], but the left number in the squared brackets is always the most significant bit of the vector.

Mixed-design Style Modeling: Here is an example of a 1-bit full-adder in a mixed-design style. module FA_Mix (A, B, input A, B, Cin; output Sum, Cout; reg Cout; reg T1, T2, T3; wire S1; xor X1 (S1, A, B); / / Gate instantiation.- Gate level modeling always @ (A or B or Cin) / / Always statement.- Structural modeling begin T1 = A & Cin; T2 =B & Cin; T3 = A & B; Cout = (T1 | T2) |T3; end assign Sum = S1^Cin;/ / Continuous assignment.- Data flow modeling endmodule

-------------------------------------------Full Adder ---------------------------module fulladd (A, B, C, sum, cout);

input A, B,C; output sum, cout; wire AB, BC, AC; xor x1 (sum, A, B,C); and a1 (AB, A,B), a2 (BC,B,C), a3 (AC, A,C); or o1 (cout, AB, BC, AC);

endmodule

-------4 Bit Ripple Carry Adder------------module rippleadder (a, b, cin, sum, cout); input [3:0] a; input [3:0] b; input cin; output [3:0]sum; output cout; wire[3:1] c; fulladd FA0 (a[0],b[0], cin, sum[0],c[1]); fulladd FA1 (a[1],b[1],c[1],sum[1],c[2]); fulladd FA2 (a[2],b[2],c[2],sum[2],c[3]); fulladd FA3 (a[3],b[3],c[3],sum[3],cout); endmodule

--------------Full Adder --------------module fulladd (A, B, C, sum, cout);

input A, B,C; output sum, cout; wire AB, BC, AC; xor x1 (sum, A, B,C); and a1 (AB, A,B), a2 (BC,B,C), a3 (AC, A,C); or o1 (cout, AB, BC, AC);

endmodule

-----------Structural Description of 2-to-4 decoder-----------------module Decoder2x4 (A,B, EN, Z); input A, B, En; output [0:3] Z; wire Abar, Bbar; not n1 (Abar, A), n2 (Bbar, B); and a1 (Z[0], Abar, Bbar, En), a2 (Z[1], Abar, B, En), a3 (Z[2], A, Bbar, En), a4 (Z[3], A, B, En); endmodule Logic Diagram

----------------D-Latch --------------------A latch is a device, used to store a single bit. The logic symbol for D-Latch is shown in Figure. module d_latch (D, Q, Qbar); input D; output Q, Qbar; wire Dbar; not n1 (Dbar, D); nor N1 (Q, Qbar, D), N2 (Qbar, Q, Dbar); endmodule

--------------------D Flip-Flop ------------------------------module d_flipflop (D, CLK,Q, Qbar); input D, CLK; output Q, Qbar; wire Dbar, x1,x2; not i1 (Dbar, D); nand N1 (x1, CLK, D), N2 (x2, CLK, Dbar), N3 (Qbar, x2, Q), N4 (Q, x1, Qbar); endmodule

--------------Full Adder --------------module fulladd (A, B, C, sum, cout);

input A, B,C; output sum, cout; wire AB, BC, AC; xor x1 (sum, A, B,C); and a1 (AB, A,B), a2 (BC,B,C), a3 (AC, A,C); or o1 (cout, AB, BC, AC);

endmodule