William Stallings Computer Organization and Architecture 8th Edition Chapter 10 & 11 Instruction Sets T1 10.1-10.5, 11.1-11.

4 R1- 2.2 (Memory Locations & Addresses), 2.5 (Addressing Modes)

Instruction Set
10.1 10.2 10.3 10.4 10.5 Machine Instruction Characteristics Types of Operands Intel x86 Data Types Types of Operations Intel x86 Operation Types

11.1 Addressing 11.2 x86 Addressing Modes 11.3 Instruction Formats 11.4 x86 Instruction Formats Summary

Objectives
To program a computer in machine or assembly language one must know about CPU registers, memory structure, supported data types, data access methods, operations supported by the ALU, and elements of the instructions & its size etc. The treatment is more generic but 8086 ISA can be use as an example.

What is an Instruction Set? The complete collection of instructions that are understood by a CPU Machine Code Binary Usually represented by assembly codes

Elements of an Instruction Operation code (Op code)

Do this

Source Operand reference

To this

Result Operand reference

Put the answer here

Next Instruction Reference

When you have done that, do this...

Instruction Representation In machine code each instruction has a unique bit pattern For human consumption (well, programmers anyway) a symbolic representation is used
e.g. ADD, SUB, LOAD

Operands can also be represented in this way

ADD A,B

Simple Instruction Format

Instruction Types Data processing Data storage (main memory) Data movement (I/O) Program flow control

3-, 2-, 1-, & 0-Address

The classification is based on arithmetic instructions that have no. of operands and one result 3-address instruction specifies memory addresses for both operands and the result R Op1 op Op2 A 2-address instruction overwrites one operand in memory with the result Op2 Op1 op Op2 A 1-address instruction has a processor, called the accumulator register, to hold one operand & the result Acc Acc op Op1 A 0-address + uses a CPU register stack to hold both operands and the result TOS TOS op SOS The 4-address instruction, hardly ever seen, also allows the address of the next instruction to specified explicitly

3-Address Instruction Format

Me m o ry O p 1 Ad d r: O p 2 Ad d r: R e s Ad d r: Op 1 Op 2 Re s CP U a d d , R e s , O p 1 , O p 2 (R e s O p 2 + O p 1 )

3 addresses
Operand 1, Operand 2, Result a = b + c; May be a forth next instruction (usually implicit) Not common Needs very long words to hold everything

Ne xtiAd d r:

Ne xti

P ro g ra m c o u n te r

24

Wh e re to find n e xt in s tru c tio n

In s tru c tio n fo rm a t B 24 O p 1 Ad d r

its :

24 R e s Ad d r Wh e re to p u t re s u lt

24 O p 2 Ad d r

a dd Wh ic h o p e ra tio n

Wh e re to fin d op e ra n d s

2-Address Instruction Format

2 addresses
Me mory
Op1Addr: Op1 CP U a dd Op2, Op1 (Op2 Op2 + Op1)

One address doubles as Op2Addr: Op2,Re s operand and result Ne xtiAddr: Ne xti a = a + b Reduces length of instruction Requires some extra work
Temporary storage to hold some results

P rogra m counte r Whe re to find ne xt ins truction

24

Ins truction forma t Bits : 8 24 Op2Addr 24 Op1Addr a dd Which ope ra tion

Whe re to find ope ra nds

Whe re to put re s ult

1-Address Instruction Format

Me m o ry O p 1 Ad d r: Op 1 CP U a d d O p 1 (Ac c Ac c + Op 1 )

Wh e re to fin d o p e ra n d 2 , a n d wh e re to p u t re s u lt
Ac c u m u la to r Ne xtiAd d r: Ne xti P ro g ra m c o u n te r 24

1 address
Implicit second address Usually a register (accumulator) Common on early machines

Need instructions to load and store operands: In s tru c tio n fo rm a t LDA OpAddr Bits : 8 24 STA OpAddr

Wh e re to fin d n e xt in s tru c tio n

a dd O p 1 Ad d r Wh ic h Wh e re to fin d o p e ra tio n o p e ra n d 1

0-Address or Stack Instruction Format

In s tru c tio n fo rm a ts Me m o ry Op 1 Ad d r: Op1 TO S S OS e tc . CP U p u s h O p 1 (TO S O p 1 ) Bits : 8 24 O p1 Ad d r R e s u lt

F o rm a t p u s h Op e ra tio n

a d d (TO S TO S + S OS ) S ta c k P ro g ra m c o u n te r Wh e re to fin d n e xt in s tru c tio n Bits : 24 F o rm a t 8

Ne xtiAd d r:

Ne xti

a dd Wh ic h o p e ra tio n

0 (zero) addresses
All addresses implicit Uses a stack

Wh e re to fin d o p e ra n d s , a n d wh e re to p u t re s u lt (o n th e s ta c k)

e.g. push a push b add pop c c=a+b

Computer must have a 1-address instruction to push and pop operands to and from the stack

Expression Evaluation for 3-, 0-Address Machines

Evaluat e a = (b+c) *d - e 3 - ad d r e s s add a, b, c mpy a, a, d sub a, a, e 2 - ad d r e s s load add mpy sub a, a, a, a, b c d e 1 - ad d r e s s load add mpy sub store b c d e a

2-, 1-, and

St a c k push push add push mpy push sub pop b c d e a

Number of instructions & number of addresses both vary Discuss as examples: size of code in each case

Problems
Write 0-, 1-, 2- and 3- address machine programs to compute X = (A+B*C) / (DE*F). Write 0-, 1-, 2- and 3- address machine programs to compute ROOT = ((b2 4ac)/2a)
0 0start: PUSH A PUSH 2 MUL PUSH C PUSH A PUSH 4 MUL MUL PUSH B PUSH B MUL SUB DIV POP SQRT(ROOT) End 1 1Start: LOAD A MUL #2 STORE T1 LOAD #4 MUL A MUL C STORE T2 LOAD B MUL B SUB T2 DIV SQRT STORE ROOT End 2 2Start: MUL B, B MOV T1, A MUL A, #4 MUL A, C SUB B, A MUL T1, #2 DIV B, T1 SQRT B, B MOV ROOT, B End 3 3Start: MUL T1, B, B MUL T2, A, C MUL T3, T2, #4 MUL T4, A, #2 SUB T5, T1, T3 DIV T6, T5, T4 SQRT ROOT, T6 End

How Many Addresses More addresses

More complex (powerful?) instructions More registers
Inter-register operations are quicker

Fewer instructions per program

Fewer addresses
Less complex (powerful?) instructions More instructions per program Faster fetch/execution of instructions

Design Decisions
Operation repertoire
How many ops? What can they do? How complex are they?

Data types Instruction formats

Length of op code field Number of addresses

Registers
Number of CPU registers available Which operations can be performed on which registers?

Addressing modes (later) RISC v CISC

Types of Operand Addresses Numbers

Integer/floating point

Characters
ASCII etc.

Logical Data
Bits or flags
(Aside: Is there any difference between numbers and characters? Ask a C programmer!)

x86 Data Types 8 bit Byte 16 bit word 32 bit double word 64 bit quad word 128 bit double quadword Addressing is by 8 bit unit Words do not need to align at evennumbered address Data accessed across 32 bit bus in units of double word read at addresses divisible by 4 Little endian

SIMD Data Types

Integer types
Interpreted as bit field or integer

Packed byte and packed byte integer

Packed word and packed word integer

Bytes packed into 64-bit quadword or 128-bit double quadword

16-bit words packed into 64-bit quadword or 128-bit double quadword

Packed doubleword and packed doubleword integer Packed quadword and packed qaudword integer

32-bit doublewords packed into 64-bit quadword or 128-bit double quadword

Two 64-bit quadwords packed into 128-bit double quadword

Packed single-precision floating-point and packed doubleprecision floating-point

Four 32-bit floating-point or two 64-bit floating-point values packed into a 128-bit double quadword

x86 Numeric Data Formats

Types of Operation Data Transfer Arithmetic Logical Conversion I/O System Control Transfer of Control

Data Transfer Specify

Source Destination Amount of data

May be different instructions for different movements

e.g. IBM 370

Or one instruction and different addresses

e.g. VAX

Arithmetic Add, Subtract, Multiply, Divide Signed Integer Floating point ? May include
Increment (a++) Decrement (a--) Negate (-a)

Shift and Rotate Operations

Logical Bitwise operations AND, OR, NOT

Input/Output May be specific instructions May be done using data movement instructions (memory mapped) May be done by a separate controller (DMA)

Systems Control Privileged instructions CPU needs to be in specific state

Ring 0 on 80386+ Kernel mode

For operating systems use

Transfer of Control Branch

e.g. branch to x if result is zero

Skip
e.g. increment and skip if zero ISZ Register1 Branch xxxx ADD A

Subroutine call
c.f. interrupt call

Branch Instruction

Nested Procedure Calls

Use of Stack

Stack Frame Growth Using Sample Procedures P and Q

Byte Order (A portion of chips?) What order do we read numbers that occupy more than one byte e.g. (numbers in hex to make it easy to read) 12345678 can be stored in 4x8bit locations as follows
Address 184
185 186 187

Value (1) 12
34 56 78

Value (2) 78
56 34 12

i.e. read top down or bottom up?

Byte Order Names The problem is called Endian The system on the left has the least significant byte in the lowest address This is called big-endian The system on the right has the least significant byte in the highest address This is called little-endian

Example of C Data Structure

StandardWhat Standard?
Pentium (x86), VAX are little-endian IBM 370, Moterola 680x0 (Mac), and most RISC are big-endian Internet is big-endian
Makes writing Internet programs on PC more awkward! WinSock provides htoi and itoh (Host to Internet & Internet to Host) functions to convert Alternative View of Memory Map

Addressing Modes Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack

Immediate Addressing
Operand is part of instruction Operand = address field e.g. ADD 5
Add 5 to contents of accumulator 5 is operand

No memory reference to fetch data Fast Limited range

Instruction Opcode Operand

Direct Addressing
Address field contains address of operand Opcode Effective address (EA) = address field (A) e.g. ADD A
Add contents of cell A to accumulator Look in memory at address A for operand
Instruction Address A

Memory

Operand

Single memory reference to access data No additional calculations to work out effective address Limited address space

Indirect Addressing Memory cell pointed to by address field contains the address of (pointer to) the operand EA = (A)
Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator

Indirect Addressing Diagram

Instruction Opcode Address A Memory

Large address space 2n where n = word length May be nested, multilevel, cascaded
e.g. EA = (((A)))
Draw the diagram yourself

Pointer to operand

Operand

Multiple memory accesses to find operand Hence slower

Register Addressing Operand is held in register named in address filed EA = R Limited number of registers Very small address field needed
Shorter instructions Faster instruction fetch

Register Addressing Diagram

Instruction Opcode Register Address R Registers

No memory access Very fast execution Very limited address space Multiple registers helps performance
Requires good assembly programming or compiler writing N.B. C programming
register int a;

Operand

c.f. Direct addressing

Register Indirect Addressing

Instruction C.f. indirect Opcode Register Address R addressing EA = (R) Registers Operand is in memory pointed to Pointer to by contents of Operand register R Large address space (2n) One fewer memory access than indirect addressing

Memory

Operand

Displacement Addressing
EA = A + (R) Address field hold two values
A = base value R = register that holds displacement or vice versa Instruction

Opcode Register R Address A

Memory

Registers

Pointer to Operand

Operand

Relative Addressing A version of displacement addressing R = Program counter, PC EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC c.f locality of reference & cache usage

Base-Register Addressing A holds displacement R holds pointer to base address R may be explicit or implicit e.g. segment registers in 80x86

Indexed Addressing A = base R = displacement EA = A + R Good for accessing arrays

EA = A + R R++

Combinations Postindex EA = (A) + (R) Preindex EA = (A+(R)) (Draw the diagrams)

Stack Addressing Operand is (implicitly) on top of stack e.g.

ADD Pop top two items from stack and add

x86 Addressing Modes

Virtual or effective address is offset into segment
Starting address plus offset gives linear address This goes through page translation if paging enabled

12 addressing modes available

Immediate Register operand Displacement Base Base with displacement Scaled index with displacement Base with index and displacement Base scaled index with displacement Relative

x86 Addressing Mode Calculation

Logical to Physical Address Calculation

The 8086 microprocessor has 20-bit address lines. All the registers in 8086 are 16-bits in length. Hence to obtain 20-bit addresses from the available 16-bit registers, all 8086 memory addresses are computed by summing the contents of a segment register and a effective memory address. 1. Given that the EA of a datum is 2359 H and the DS = 490B H, what is the physical address of the datum? DS: 490B0 H EA: 2359 H Physical add. 4B409 2. If a physical branch address is 5A230 H when (CS) = 5200 H, what will be PA if the (CS) are changed to 7800 H. CS: 52 0 0 EA: XXXX Physical add. 5A2 3 0 H Hence EA = Physical add - (Segment address displaced by 4bits) EA = 5A230 - 52000 = 8230 H If the CS is changed to 7800 H the Physical address will be 78000 + 8230 = 80230

Instruction Formats
Layout of bits in an instruction Includes opcode Includes (implicit or explicit) operand(s) Usually more than one instruction format in an instruction set

Instruction Length
Affected by and affects:
Memory size Memory organization Bus structure CPU complexity CPU speed

Trade off between powerful instruction repertoire and saving space

Allocation of Bits
Number of addressing modes Number of operands Register versus memory Number of register sets Address range Address granularity

x86 Instruction Format

Summary
Machine Instruction Characteristics Types of Operands Intel x86 Data Types Types of Operations Intel x86 Operation Types Addressing x86 Addressing Modes Instruction Formats x86 Instruction Formats