Phase Locked Loop (PLL)

Study, Modeling & Simulation in MATLAB Mohammad A Maktoomi

Where Do We Need em ?

CPU Clock

Crystal Oscillator

PLL

USB

DVD Drive

VCO or PLL ?
Freq

Vcont

Needs very precise/stable voltage Temperature/Process variations Phase Noise Impact more pronounce

PLL
A Phase Locked Loop (PLL) is a negativefeedback control system that matches the phase of a locally generated (within the system) signal to that of an external (input to the system) signal. The real aim of (most) PLL applications is to obtain an output frequency which is matched to the input frequency (Why not FLL, then?).

PLL VS FLL !

Vin Vout due to various non-idealities ! Thus, Fin Fout (in hypothetical FLL)!
However, in PLL even if in-out0, Frequency may be Locked: Fin = Fout

A BASIC PLL

The Phase Detector (PD) compares the phases from the input (Vin) and output (Vout) signals and sends a decision (VPD) to the Voltage Controlled Oscillator (VCO).
XOR as PD

PD

VCO
As implied by the name, the VCO takes as input a voltage and outputs a proportional frequency. Again, the relationship is linear and given by:
Freq

Vcont

TYPE-I PLL Model

Problems with Type-I PLL

* is directly proportional to LPF. A low value of LPF is required for lower ripple implying a low value of which leads to more settling time ! Also, if the reference frequency and the VCO frequency a widely apart, locking may not occur at all (Loop locks only when input and vco frequencies differ by less than LPF.

PFD
Bring frequency Closer using FD Then work as usual with PD Aided acquisition !

PFD

PFD/CP

PFD/CP with modified filter

Integer-N Synthesizers
PFD/CP

LPF

VCO

N fREF=fout/N fout=N fREF

Fractional-N Synthesizers
PFD/CP

LPF

VCO

N
11 10
NOT FIXED

Phase Noise

THANKS