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Design Consideration
Opertaing frequency -
1
2
Input matching (Sweeping Lg)
Output matching (Sweeping Rd, Cout)
Cascode stage Gain rises due to sammation
of the transconductances gm of two MOSFETs.
Biasing Voltage For power consideration
BalUn Circuit
Gain (s21db)
s11 and s22
Reverse isolation parameter (s12)
Noise Figure
Power and IIp3
Summary
Parameters Value
Gain 12.7 dB
Center Frequency
4.5 GHz
Bandwidth 1.41 GHz
Power Consumption 10.5 mW
IIP3 -35
1 dB compression point -25 dBm
Noise Figure 1.65dB
Digital Filter
Digital filters are used to remove noise and
other unwanted signal components.
Two common architecture
(i) Finite Impulse Response (FIR)
(ii) Infinite impulse Response (IIR)
FIR Filter
Impulse response is of finite duration.
Output is a weighted sum of the current and a
finite number of previous values of the input.
Moving average filters as output at any time
index depends on a window containing only
the most recent N samples of the input
FIR x[n]
y[n]
FIR Filter
Output sequence in terms of input x(n) can be
written as
x(n) = Input signal
y(n) = Output signal
N = Filter order
b = Filter coefficient
FIR Filter
Matlab Code
clear all;
clc;clf;
format long
fs=48000; %Sampling Frequency
%Hamming Window Filter
b=fir1(8,0.6) %cutoff frequency=0.6*48/2= 14.4kHz
freqz(b,1,200,fs)
range=max(b)-min(b);
interval_size=range/128;
partition=[min(b)+interval_size:interval_size:max(b)];
codebook=[0:127];
quants = quantiz(b,partition,codebook) %Quantized filter coefficients
n=0:100;
x=sin(2*pi*n*500/fs)+sin(2*pi*n*18000/fs);
figure
subplot(2,1,1), stem(n,x);xlabel('Sampling Number(n)');ylabel('Input(x)');
y=filter(b,1,x);
subplot(2,1,2), stem(n,y);xlabel('Sampling Number(n)');ylabel('Output(y)');
Magnitude and Phase Response
Coefficients from MATLAB
Verilog Code
module FIR_Hamming_Lowpass (Data_out, Data_in, clock, reset);
parameter order = 8;
parameter word_size_in = 8;
parameter word_size_out = 2*word_size_in+2;
parameter b0=8'd11;
parameter b1=8'd7;
parameter b2=8'd0;
parameter b3=8'd61;
parameter b4=8'd127;
parameter b5=8'd61;
parameter b6=8'd0;
parameter b7=8'd7;
parameter b8=8'd11;
output[word_size_out-1:0] Data_out;
input[word_size_in-1:0] Data_in;
input clock, reset;
reg [word_size_in-1:0] Samples[1:order];
integer k;
assign
Data_out=b0*Data_in+b1*Samples[1]+b2*Samples[2]+b3*Samples[3]+b4*Samples[4]+b5*Samples[5]+b6*Samples[6]+b7*Samples[7]+
b8*Samples[8];
always @ (posedge clock)
if (reset==1) begin for (k=1;k<=order;k=k+1) Samples [k]=0; end
else begin
Samples[1]<=Data_in;
for (k=2;k<=order;k=k+1) Samples[k]<=Samples[k-1];
end
endmodule
RTL Diagram
Input and Output
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