Low Power

Digital Integrated Circuits
2nd
Inverter
POWER
Introduction to Low Power
VLSI Design
Dr Anu Mehra
2nd
Inverter
Where Does Power Go in CMOS?
Dynamic Power Consumption
Short Circuit Currents
Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
2nd
Inverter
Power dissipation can be
dynamic
due to capacitive switching
short circuit power due to crowbar currents
Glitches in output waveform
Static
leakage currents
sub threshold current + reverse bias
standby current pseudo nmos

2nd
Inverter
Dynamic Power
Charging and discharging of
capacitors due to logic
switching event
2nd
Inverter
Each time the input switches from 0to 1
or 1 to 0 power is consumed.
PART IS DISSPATED in charging and
discharging the capacitor
PART IS STORED in the load capacitor
2nd
Inverter
Dynamic Power Dissipation
Energy/transition = C
L
* V
dd
2
Power = Energy/transition * f = C
L
* V
dd
2
* f
0

to1 or 1 to 0
Need to reduce C
L
, V
dd
, and f to reduce power.
Vin Vout
C
L
Vdd
Not a function of transistor sizes!
i
VDD
f
0 to1 or 1 to 0
is the frequency of transition

2nd
Inverter
2
0 0 0
) (
DD L
VDD
out DD L
out
L DD DD VDD VDD
V C dv V C dt
dt
dv
C V dt V t i E = = = =
} } }

2
) (
2
0 0 0
DD L
VDD
out out L out
out
L out VDD C
V C
dv v C dt v
dt
dv
C dt v t i E = = = =
} } }

Half the energy stored in the Capacitor,
the other half is lost !
2nd
Inverter
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E
N
C
L
V
dd
-
2
n N ( ) - =
n(N): the number of 0->1 transition in N clock cycles
E
N
: the energy consumed for N clock cycles
P
avg
N
lim
E
N
N
-------- f
clk
- =
n N ( )
N
------------
N
lim
\ .
| |
C -
L
V
dd
-
2
f
clk
- =
o
0 1
n N ( )
N
------------
N
lim =
P
avg
= o
0 1
C -
L
V
dd
-
2
f
clk
-
2nd
Inverter
Transistor Sizing for Minimum Energy
A quick review of delay
2nd
Inverter
Delay Formula
C
int
= C
gin
with

~ 1
f = C
ext
/C
gin
- effective fanout
C
ext
=fC
gin
R = R
unit
/W ; C
int
=WC
unit

t
p0
= 0.69R
unit
C
unit
Let tp=0.69 Req(Cint+Cext)
=0.69 ReqCint(1+Cext/Cint)
=tp0(1+Cext/Cint)
=tp0(1+f/)
2nd
Inverter
Transistor Sizing for Minimum
Energy
Goal: Minimize Energy of whole circuit
Design parameters: f and V
DD

tp s tpref of circuit with f=1 and V
DD
=V
ref
1
C
g1
In
f
C
ext
Out
TE DD
DD
p
p p
V V
V
t
f
F f
t t
|
|
.
|
\
|
|
|
.
|
\
|
+ +
|
|
.
|
\
|
+ =
0
0
1 1

2nd
Inverter
Delay as a function of V
DD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
DD
(V)
t
p
(
n
o
r
m
a
l
i
z
e
d
)
2nd
Inverter
Total Capacitance of inverter chain is
Cg1+Cint1+Cext1+Cint2+Cext2
=Cg1+Cg1+fCg1+fCg1+FCg1
=Cg1(1++f+f+F)
E=V
DD
2
(total

capacitance)
2nd
Inverter
Transistor Sizing (2)
Performance Constraint (=1)

Energy for single Transition

( ) ( )
1
3
2
3
2
0
0
=
+
|
|
.
|
\
|
+ +
=
+
|
|
.
|
\
|
+ +
=
F
f
F
f
V V
V V
V
V
F
f
F
f
t
t
t
t
TE DD
TE ref
ref
DD
ref p
p
pref
p
( )( ) | |
|
.
|
\
|
+
+ +
|
|
.
|
\
|
=
+ + + =
F
F f
V
V
E
E
F f C V E
ref
DD
ref
g DD
4
2 2
1 1
2
1
2

2nd
Inverter
(
|
|
.
|
\
|
+ +
|
|
.
|
\
|
+ =
f
F f
tp tp

1 1 0
(
+ + =
=
f
F
f tp 2
1
Let for a reference device f=1
2nd
Inverter
( )
( )
ref
DD
TE DD
TE ref
TE ref
ref
TE DD
DD
V
V
V V
V V
ref tp
tp
V V
V
ref tp
V V
V
tp
F ref tp
f
F
f tp
tpref
tp
F ref tp tpref
~
+
|
|
.
|
\
|
+ +
=
+ =
0
0
0
0
3 0
2 0
3 0
2nd
Inverter
1 2 3 4 5 6 7
0
0.5
1
1.5
2
2.5
3
3.5
4
f
v
d
d

(
V
)
1 2 3 4 5 6 7
0
0.5
1
1.5
f
n
o
r
m
a
l
i
z
e
d

e
n
e
r
g
y
Transistor Sizing (3)
F=1
2
5
10
20
V
DD
=f(f)
E/E
ref
=f(f)
2nd
Inverter
Also called crowbar currents
Refers to direct path from
V
DD
to V
GND
during switching
events

scr is short circuit rise time
And scf is short circuit fall time
P
SC
is short circuit power consumption
I
SC
is the short circuit current consumed
t
sc
is the duration for which the short circuit
current flows
I
SC
,avg is the average crowbar current during
rise and fall.

2nd
Inverter
C
sc
is short
circuit
capacitance

clk
f
T
=
1
2nd
Inverter
Short Circuit Currents- another approach
Rise/Fall time of input wave is greater than 0, so short
circuit current will flow
Let VTn=VTp=VT
Consider 0 to 1 transition. Initially when Vin was 0,
pmos was on and nmos was off
As point 1 approaches nmos is turned on as Vin =VT.
pmos is still on
Short circuit current flows from VDD to GND
Current increases to maximum when both devices
enter saturation
As point 2 approaches, pmos shuts down, crowbar
current stops flowing

V
T
VDD-V
T
1
2
time
voltage
2nd
Inverter
Direct Path currents contd.
Area of an equilateral triangle is
1/2base. perpendicular
P=VI, E=Pt
2nd
Inverter
f
0

to1 or 1 to 0 is
switching frequency
ts is 0 to 100% transition time
tr(f) is 10 to 90% transition time

2nd
Inverter
How to minimize crowbar currents?
Consider a CMOS inverter with a 0 to 1 transition at the input
Let C
L
be very large
Thus, output will make a a 1 to 0 transition t
f
=0.69R
N
C
L
This delay will also be large
Assume that input rise time is very small
Input will change through transition before output changes
Vs of pmos is at VDD
VD of pmos will be approximately at VDD
Thus VDS of pmos is approx 0
Device shuts off before delivering any current

2nd
Inverter
How to minimize crowbar currents?
Consider again a CMOS inverter with a 0 to 1 transition at the
input
Let C
L
be very small
Thus, output will make a a 1 to 0 transition t
f
=0.69R
N
C
L
This delay will also be small
Assume that input rise time is very large
Input will change through transition slowly
Vs of pmos is at VDD
VD of pmos will be approximately at 0
Thus VDS of pmos is approx VDD
Maximum short circuit current is
delivered

2nd
Inverter
Vin Vout
C
L
Vdd
I
V
D
D

(
m
A
)
0.15
0.10
0.05
V
in
(V)
5.0 4.0 3.0 2.0 1.0 0.0
2nd
Inverter
How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if t
fall
>> t
rise
,
but cant do this for cascade logic, so ...
Input
slope is
fixed
2nd
Inverter
Conclusion
Large C
L
may mean less short circuit power, but it
will also mean longer delays
Will lead to short circuit currents in fan out gate as
their tin will be slow!!
Local Optimization pointless!
To minimize power consumption in a global way
Match rise/fall times of input and
output waveforms
2nd
Inverter
Minimizing Short-Circuit Power
0 1 2 3 4 5
0
1
2
3
4
5
6
7
8
t
sin
/t
sout
P
n
o
r
m
Vdd =1.5
Vdd =2.5
Vdd =3.3
2nd
Inverter
Notice in the previous graph that when tsin/tsout=1 Power
Dissipation is minimum
Reducing V
DD
leads to lower power consumption

Point 1 is VTn Point2 is VDD-VTP
If 2 lies before 1 short circuit power consumption is 0!
However circuit will be slower

V
T
VDD-V
T
1
2
time
voltage
2nd
Inverter
Dynamic Power -Glitches
Glitches are caused by arrival time of two separate input signals. If a given
input signal arrives first and causes the output to switch, later another input
signal arrives and causes the output to switch back to original value.
Undesired Power dissipation ! Glitches propagate thought the fanout gate and
cause further unintended transitions
2nd
Inverter
To reduce glitches,
Signals should be made to arrive at
roughly the same time
Certain architectures and logics are
made glitch free inherently
2nd
Inverter
Static Power Consumption
Caused by leakage currents due to
Reverse biased Source and drain junctions
Subthreshold currents and ie currents that
flow when VGS is less than VT
2nd
Inverter
Leakage
Vout
Vdd
Sub-Threshold
Current
Drain Junction
Leakage
Sub-Threshold Current Dominant Factor
Sub-threshold current one of most compelling issues
in low-energy circuit design!
2nd
Inverter
Reverse-Biased Diode Leakage
N
p
+ p
+
Reverse Leakage Current
+
-
V
dd
GATE
I
DL
= J
S
A
J
S

= 1-5pA/m
2
for a 1.2m CMOS technology
J
s
double with every 9
o
C increase in temperature
J S =10-100 pA/m2 at 25 deg C for 0.25m CMOS
J S doubles for every 9 deg C!

2nd
Inverter
Junction Leakage currents are caused
by thermally generated carriers. Their
value increases with increasing
temperature. At 85 degrees Celsius,
(upper bound for junction temperature)
their value increases by 60 times over
room temperature value.
2nd
Inverter
Subthreshold Leakage Component
2nd
Inverter
Sub threshold Leakage issues
Closer V
T
is to 0 V, larger is the static power
dissipation as I
D
becomes larger
L is getting smaller as source and drain are getting
closer
Supply voltages are being scaled while keeping V
T
constant. This leads to increase in delay see next
slide. As Supply voltage goes down to 2V
T,,
performance goes down substantially.
If V
T
is lowered, performance improves, sub threshold
leakage becomes an issue
i.e. Trade off between power and delay!
2nd
Inverter
Delay as a function of V
DD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
DD
(V)
t
p
(
n
o
r
m
a
l
i
z
e
d
)
V
T
=0.5V
2nd
Inverter
Static Power Consumption
V
in
=5V
V
out
C
L
Vdd
I
stat
P
stat
= P
(In=1)
.V
dd
. I
stat
Dominates over dynamic consumption
Not a function of switching frequency
Wasted energy
Should be avoided in almost all cases,
but could help reducing energy in others (e.g. sense amps)
2nd
Inverter
Principles for Power Reduction
Prime choice: Reduce voltage!
Recent years have seen an acceleration in
supply voltage reduction
Design at very low voltages still open
question (0.6 0.9 V by 2010!)
Reduce switching activity
Reduce physical capacitance
Device Sizing: for F=20
f
opt
(energy)=3.53, f
opt
(performance)=4.47
2nd
Inverter
Modification for Circuits with Reduced Swing
C
L
V
dd
V
dd
V
dd
-V
t
E
0 1
C
L
V
dd
V
dd
V
t
( ) - - =
Can exploit reduced swing to lower power
(e.g., reduced bit-line swing in memory)
2nd
Inverter
Power Equation
Static power loss in pseudo
nmos only half the time!
2nd
Inverter
POWER DELAY TRADE OFF
We want low power and small delay. Why not minimize the product?
P
avg
is average Power consumed
t
p
is average delay
Only dominant term
in Power Equation
Assume Gate switches at
maximum possible rate so rise
and fall
2nd
Inverter
To Reduce PDP
Reduce Load Capacitance
Reduce Supply Voltage
PDP does not capture the fact that reducing
Supply Voltage lowers Power consumption,
but increases delay
New metric Energy Delay Product is defined
(EDP)
EDP=PDPt
p

2nd
Inverter
Differentiating EDp w.r.t. V
DD
and
putting the result equal to 0
2nd
Inverter
V
DD
(V)
V
T
=0.5V
2nd
Inverter
LPVD Lecture-1

Three components :
Dynamic Capacitive (Switching) Power:
- Charging and Discharging the capacitance.
- Still dominant component in current technology.
Short-circuit Power:
- Due to current flow from Vdd to GND.
- Worst in case of slow transition.
Leakage Current:
- Diodes Leakage around transistor and N-well.
- Increases 20 times for each new technology.
- Becoming insignificant to the dominant factor.

SOURCES OF POWER DISSIPATION
2nd
Inverter
LPVD Lecture-1

Reduced switching voltage:

- P=CfV
2
Saving in power but performance is lost.
- Transistors become slow due to low V
t
, leakage
current increases. Noise margins problem increases.
Reduced leakage and Static Current:
- Can be reduce by transistor sizing, layout techniques,
and careful circuit design.
- Circuit models can be turned off if not in used.
Use Standby Mode :
- Clock disabling and power-off of selected logic
blocks.

LOW POWER APPROACHES
2nd
Inverter
LPVD Lecture-1

Reduced Switching Capacitance:

- Can not reduce blindly. Reduce product of cap and
switching frequency.
- Signals with high switching frequency are routed with
minimum parasitic cap.
- Node with large Capacitance are not allowed to switch
at high frequency.
-capacitance reduction is achieved at different level.
Material, technology, physical design, circuit technique.

2nd
Inverter
LPVD Lecture-1

Reduced switching Frequency:
- Eliminate logic switching that is not necessary for
computation to reduce the frequency.
- Change the logic family, use different coding method,
number representation system. They can alter the
switching frequency of the design
Adiabatic Computing :
- Avoid gain / loss of heat during computing.

2nd
Inverter
Thank you .

Low Power

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