Design For Test

Copyright 2004 Mani Srivastava
Design for Test

EE116B (Winter 2004): Lecture # 5
Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: http://www.ee.ucla.edu/~mbs
VLSI Realization Process

Customers need Determine requirements Write specifications Design synthesis and Verification Test development
Fabrication
Manufacturing test Chips to customer
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
Definitions
Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.
Validation and Test of Manufactured Circuits
Goals of Design-for-Test (DFT)
make testing of manufactured part swift & comprehensive provide controllability and observability
DFT mantra
Components of DFT strategy

provide circuitry to enable test provide test patterns that guarantee reasonable coverage
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
Test Classification
Diagnostic test

used in chip/board debugging defect localization used to determine whether a chip is functional simpler than diagnostic test; must be simple & swift x e [v,i] versus x e [0,1] check parameters such as NM, Vt, tp, T
Go/no-go or production test

Parametric test (static/dc and dynamic/ac tests)

Verification vs. Test
Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design.
Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices.
Why such a big deal?
High speed testers are astronomically costly! Reducing test time can help increase throughput of tester
impacts testing cost
Testing must be considered from early phases of the design process
Costs of Testing
Design for testability (DFT)

Chip area overhead and yield reduction Performance overhead
Software processes of test

Test generation and fault simulation Test programming and debugging
Manufacturing test
Automatic test equipment (ATE) capital cost Test center operational cost
Design for Testability (DFT)

DFT refers to hardware design styles or added hardware that reduces test generation complexity.
Motivation: Test generation complexity increases exponentially with the size of the circuit. Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks. Logic block A
PI Test input
Int. bus
Logic block B
PO
Test output
10
Present and Future

1997 -2001 2003 - 2006
Feature size (micron) 0.25 - 0.15 0.13 - 0.10 Transistors/sq. cm 4 - 10M 18 - 39M
Pin count Clock rate (MHz) Power (Watts)
100 - 900 200 - 730 1.2 - 61
160 - 1475 530 - 1100 2 - 96
* SIA Roadmap, IEEE Spectrum, July 1999

11
Cost of Manufacturing Testing in 2000AD
0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price
= $1.2M + 1,024 x $3,000 = $4.272M = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second
Running cost (five-year linear depreciation)

Test cost (24 hour ATE operation)

12
Roles of Testing
Detection: Determination whether or not the device under test (DUT) has some fault. Diagnosis: Identification of a specific fault that is present on DUT. Device characterization: Determination and correction of errors in design and/or test procedure. Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.
13
Design for Testability

N inputs N inputs Combinational Logic Module K outputs Combinational Logic Module K outputs
M state regs (a) Combinational function (b) Sequential engine
2N patterns
2N+M patterns
Exhaustive test is impossible or unpractical

(consider a processor with N=64, M=50 at 1 sec/pattern)
14
Testing Approach
Exhaustive testing has redundancy
same fault covered by many input patterns

only one needed, other are superfluous
Cost of detecting all patterns may not be worth it
typical test procedures attempt 95-99% coverage
15
Ideal vs. Real Tests
Ideal tests detect all defects produced in the manufacturing process. Ideal tests pass all functionally good devices. Very large numbers and varieties of possible defects need to be tested. Difficult to generate tests for some real defects. Defectoriented testing is an open problem.
Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.
16
Testing as Filter Process

Good chips Prob(good) = y
Prob(pass test) = high
Mostly good chips
Fabricated chips Mostly bad chips
Defective chips Prob(bad) = 1- y
Prob(fail test) = high
17
A Modern VLSI Device System-on-a-chip (SOC)

DSP core Data terminal Interface logic RAM ROM Mixedsignal Codec
Transmission medium
18
Testing Principle
19
Problem: Controllability & Observability
Combinational circuits

controllable and observable relatively easy to determine test patterns turn into combination circuits or, use self-test use self-test
Sequential circuits: have state!

Memory: requires complex patterns
20
Test Approaches
Three approaches

Ad-hoc testing Scan-based testing Self-test increasing complexity and heterogeneous combination of modules in systems-on-a-chip advanced packaging and assembly techniques extend problem to the board level
Problem is getting harder
21
Generating and Validating Test-Vectors
Automatic test-pattern generation (ATPG)
for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output majority of available tools: combinational n/w only sequential ATPG available from academic research
determines test coverage of proposed test-vector set simulates correct network in parallel with faulty networks
Fault simulation

Both require adequate models of faults in CMOS
22
Fault Modeling
Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults

Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at faults and multiple faults
Transistor faults
23
Why Model Faults?
I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments
24
Some Real Defects in Chips

Processing defects Missing contact windows Parasitic transistors Oxide breakdown . . . Material defects Bulk defects (cracks, crystal imperfections) surface impurities (ion migration) . . . Time-dependent failures Dielectric breakdown Electromigration . . . Packaging failures Contact degradation Seal leaks . . .
Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation Semiconductor Devices and Circuits, Wiley, 1981.
25
Observed PCB Defects

Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) 51 1 6 13 6 8 5 5 5
Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

26
Common Fault Models
Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults
27
Fault Models
Most Popular - Stuck - at model
0 1
sa0 (output)
sa1 (input)
Covers almost all (other) occurring faults, such as opens and shorts.
Z
x1
x3
x2
[Adapted from http://infopad.eecs.berkeley.edu/~icdes ign/. Copyright 1996 UCB]
, : x1 sa1 : x1 sa0 or x2 sa0 : Z sa1
28
Single Stuck-at Fault
Three properties define a single stuck-at fault

Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate
Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value
c
1 0
Good circuit value
a b
d
e f
s-a-0
0(1) 1(0) 1
g
1
h i k
Test vector for h s-a-0 fault
29
Fault Equivalence
Number of fault sites in a Boolean gate circuit = #PI + #gates + #(fanout branches). Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuits can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.
30
Equivalence Rules
sa0 sa0 sa1
sa0 sa1
sa1
sa0 sa1
AND
sa0 sa1
sa0 sa1 sa0 sa1
OR
sa0 sa1
WIRE
sa0 sa1 sa0 sa1 sa0 sa1
NOT
sa1 sa0
NAND
sa0 sa1
sa0 sa1 sa0 sa1
NOR
sa0 sa1 sa0 sa1
sa0 sa1 sa0 sa1
FANOUT
31
Equivalence Example
sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----- = 0.625 32 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 Faults in red removed by equivalence collapsing
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
32
Fault Dominance
If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1. Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list. When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. See the next example. In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set. If two faults dominate each other then they are equivalent.
33
Dominance Example
All tests of F2 F1 s-a-1 F2 s-a-1 001 110 101 010 011
000
100
s-a-1 s-a-1
Only test of F1
s-a-1 s-a-0 A dominance collapsed fault set

34
Checkpoints

Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit.
Total fault sites = 16 Checkpoints ( ) = 10
35
Classes of Stuck-at Faults
Following classes of single stuck-at faults are identified by fault simulators:
Potentially-detectable fault -- Test produces an unknown (X) state at PO; detection is probabilistic, usually with 50% probability. Initialization fault -- Fault prevents initialization of the faulty circuit; can be detected as a potentially-detectable fault. Hyperactive fault -- Fault induces much internal signal activity without reaching PO. Redundant fault -- No test exists for the fault. Untestable fault -- Test generator is unable to find a test.
36
Multiple Stuck-at Faults
A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values. The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k-1. A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare. Statistically, single fault tests cover a very large number of multiple faults.
37
Transistor (Switch) Faults
MOS transistor is considered an ideal switch and two types of faults are modeled:
Stuck-open -- a single transistor is permanently stuck in the open state. Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage.
Detection of a stuck-open fault requires two vectors. Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ).
38
Problem with stuck-at model: CMOS open fault

x1 Z x1 x2 x2
Sequential effect
Needs two vectors to ensure detection! Other options: use stuck-open or stuck-short models This requires fault-simulation and analysis at the switch or transistor level - Very expensive!
39
Another Stuck-Open Examples

pMOS FETs 1 0
Vector 1: test for A s-a-0 (Initialization vector) Vector 2 (test for A s-a-1)
VDD
0
0
A B
Stuckopen
Two-vector s-op test can be constructed by ordering two s-at tests
1(Z) Good circuit states
nMOS FETs
Faulty circuit states
40
Problem with stuck-at model: CMOS short fault

0 C D 0 A B
Causes short circuit between Vdd and GND for A=C=0, B=1 Possible approach: Supply Current Measurement (IDDQ) but: not applicable for gigascale integration
41
Another Stuck-Short Example

Test vector for A s-a-0 pMOS FETs 1 0
VDD
Stuckshort
A B
IDDQ path in faulty circuit
Good circuit state

0 (X)
nMOS FETs
Faulty circuit state
42
Summary of Fault Models
Fault models are analyzable approximations of defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technology-dependent faults require special tests. Memory and analog circuits need other specialized fault models and tests.
43
Automatic Test Pattern Generation
Determine a minimum set of excitation vectors that cover a significant portion of the fault set as defined by the adopted fault model An approach: start form random set of patterns
use fault simulation to determine how many potential faults are detected iteratively add or remove extra vectors determines fault coverage correct circuit simulated in parallel with a number of faulty ones, each with a single fault
results compared
Fault simulation

44
Exhaustive Test Pattern Generation
For n-input circuit, generate all 2n input patterns Infeasible, unless circuit is partitioned into cones of logic, with 15 inputs
Perform exhaustive ATPG for each cone Misses faults that require specific activation patterns for multiple cones to be tested
45
Random-Pattern Generation
Flow chart for method Use to get tests for 60-80% of faults, then switch to Dalgorithm or other ATPG for rest
46
Fault Simulation
Fault simulation Problem: Given

A circuit A sequence of test vectors A fault model Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults Determine test quality and in turn product quality Find undetected fault targets to improve tests
Determine
Motivation

47
Fault Simulator in a VLSI Design Process

Verified design netlist Fault simulator Verification input stimuli Test vectors
Modeled Remove fault list tested faults Fault coverage ?
Test Delete compactor vectors
Low
Test generator
Add vectors
Adequate Stop
48
Fault Simulation Algorithms
Serial Parallel Concurrent Deductive Differential
49
Serial Algorithm
Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list:

Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses with saved responses If response differs, report fault detection and suspend simulation of remaining vectors
Advantages:
Easy to implement; needs only a true-value simulator, less memory Most faults, including analog faults, can be simulated
50
Serial Algorithm (Cont.)
Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits Alternative: Simulate many faults together
Fault-free circuit
Circuit with fault f1 Comparator Circuit with fault f2 f2 detected? Comparator f1 detected?
Test vectors
Comparator Circuit with fault fn
fn detected?
51
Parallel Fault Simulation
Best with two-states (0,1) Exploits inherent bit-parallelism of logic operations on computer words Storage: one word per line for two-state simulation Multi-pass simulation: Each pass simulates w-1 new faults, where w is the machine word length Speed up over serial method ~ w-1 Not suitable for circuits with timing-critical and nonBoolean logic
52
Parallel Fault Sim. Example

Bit 0: fault-free circuit Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1

1 1 1
a
b
1 1 1 1 0 1
1 0 1
c s-a-0 detected
e
0 0 0
s-a-0
1 0 1
s-a-1
0 0 1
55
Concurrent Fault Simulation
Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault-free circuit. A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any. All events of fault-free and all faulty circuits are implicitly simulated. Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.) Faster than other methods, but uses most memory.
56
Conc. Fault Sim. Example

0 1
a0
0
1 0
b0
0
c0
0
1 1
e0
0
a b
1 1 1 1 1
c d
e
0
1 0
g
0 1
1 0
0 0
a0
0
b0
0 0 1 1
c0
0
0 0 1 1
e0
0
b0
d0
f1
g0
f1
d0
57
Fault Sampling
A randomly selected subset (sample) of faults is simulated. Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage: Saving in computing resources (CPU time and memory.) Disadvantage: Limited data on undetected faults.
58
Motivation for Sampling
Complexity of fault simulation depends on:

Number of gates Number of faults Number of vectors
Complexity of fault simulation with fault sampling depends on:

Number of gates Number of vectors
59
Functional vs. Structural ATPG
60
Carry Circuit
61
Functional vs. Structural (Continued)
Functional ATPG generate complete set of tests for circuit inputoutput combinations 129 inputs, 65 outputs: 2129 = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns Using 1 GHz ATE, would take 2.15 x 1022 years Structural test: No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) Takes 0.000001728 s on 1 GHz ATE Designer gives small set of functional tests augment with structural tests to boost coverage to 98+ %
62
Automatic Test Pattern Generation: Path Sensitization

Goals: Determine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes) 1 1 sa0 1 1 0
Out
Fault enabling
1 1 Fault propagation 0
Techniques Used: D-algorithm, Podem
63
Path Sensitization Method Circuit Example

1 Fault Sensitization 2 Fault Propagation 3 Line Justification
64
Using 5-Valued Logic

Symbol D D 0 1 X
Meaning 0/1 1/0 0/0 1/1 X/X Good Machine 0 1 0 1 X Failing Machine 1 0 0 1 X
Represent two machines, which are simulated simultaneously: Good circuit machine (1st value) Bad circuit machine (2nd value)
65

Try path f h k L blocked at j, since
there is no way to justify the 1 on i
1 1 D D D
1
66

Try simultaneous paths f h k L and
g i j k L blocked at k because Dfrontier (chain of D or D) disappears
1 1 D D 1
67

Final try: path g i j k L test found!
0 1
0
D D D
1 1
68
Irredundant Hardware and Test Patterns
Combinational ATPG can find redundant (unnecessary) hardware
Fault a sa1, b sa0 a sa0, b sa1
Test A=1 A=0
Therefore, these faults are not redundant
69
Redundant Hardware and Simplification
70
Redundant Fault q sa1
71
Multiple Fault Masking
f sa0 tested when fault q sa1 not there
72
Multiple Fault Masking
f sa0 masked when fault q sa1 also present
73
Ad-hoc Test
Memory
address data data
Memory
address
test
select
Processor Processor
I/O bus I/O bus
Inserting multiplexer improves testability

74
Design-for-Testability
Extra hardware

no functionality other than to improve testability take penalty in area and performance if observability and controllability improved e.g. Test port multiplex test andn ormal signals on same pins
Extra I/O pins

75
Scan-based Test
ScanIn ScanOut Out
Register
Logic A
Register
In
Combinational
Combinational Logic B
76
Scan-based Test: Operation

In 0 Test ScanIn Latch Test Test In1 Test Test In2 Test Test In 3 Test ScanOut Latch Latch Latch
Out0
Out1
Out2
Out3
Test 1 2 N cycles scan-in 1 cycle evaluation N cycles scan-out
77
Polarity-Hold SRL (Shift-Register Latch)

System Data D L1 Q SO Shift B Clock B L2 SO System Clock C SI Scan Data Shift A Clock A Q
Level sensitive Scan Design (LSSD) Introduced at IBM and set as company policy
78
Scan-Path Register
OUT SCAN SCANIN PHI2 PHI1 SCANOUT
IN
LOAD
KEEP
79
Scan-Path Testing
A REG[1] B REG[0] SCANIN REG[2] REG[3]
REG[4] COMPIN COMP
REG[5]
SCANOUT
Partial-Scan can be more effective for pipelined datapaths

OUT
80
Boundary Scan (JTAG or IEEE1149)

Printed-circuit board Logic Packaged IC
normal interconnect
Scan-in Scan-out
si
so scan path
Bonding Pad
Board testing becomes as problematic as chip testing

81
Built-in Self-test (BIST)

(Sub)-Circuit Stimulus Generator Under Test Response Analyzer
Test Controller
Rapidly becoming more important with increasing chip-complexity and larger modules
82
Linear-Feedback Shift Register (LFSR)

R S0 1 0 1 1 1 0 0 1 R S1 0 1 0 1 1 1 0 0 R S2 0 0 1 0 1 1 1 0
Pseudo-Random Pattern Generator: 2N-1 states

83
Signature Analysis
In Counter R
Counts transitions on single-bit stream Compression in time
84
BILBO
B0 B1 ScanIn ScanOut R S0 R S1 R S2
mux
D0
D1
D2
B0 B1 1 0 1 0 1 0 0 1
Operation mode Normal Scan Pattern generation or Signature analysis Reset

85
BILBO Application
ScanIn ScanOut
BILBO-A
Logic
BILBO-B
In
Combinational
Combinational Logic
Out
86
Memory Self-test
data -in Memory FSM Under Test address & R/W control Analysis data-out Signature
Patterns: Writing/Reading 0s, 1s, Walking 0s, 1s Galloping 0s, 1s


Design For Test

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Design For Test

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Copyright 2004 Mani Srivastava

Design for Test

Copyright 2004 Mani Srivastava

VLSI Realization Process

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Copyright 2004 Mani Srivastava

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Copyright 2004 Mani Srivastava

Validation and Test of Manufactured Circuits

Goals of Design-for-Test (DFT)

Components of DFT strategy

Copyright 2004 Mani Srivastava

Go/no-go or production test

Parametric test (static/dc and dynamic/ac tests)

Copyright 2004 Mani Srivastava

Verification vs. Test

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Copyright 2004 Mani Srivastava

Why such a big deal?

impacts testing cost

Testing must be considered from early phases of the design process

Copyright 2004 Mani Srivastava

Design for testability (DFT)

Software processes of test

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Copyright 2004 Mani Srivastava

Design for Testability (DFT)

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Copyright 2004 Mani Srivastava

Present and Future

Pin count Clock rate (MHz) Power (Watts)

100 - 900 200 - 730 1.2 - 61

160 - 1475 530 - 1100 2 - 96

* SIA Roadmap, IEEE Spectrum, July 1999

Copyright 2004 Mani Srivastava

Cost of Manufacturing Testing in 2000AD

0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price

Running cost (five-year linear depreciation)

Test cost (24 hour ATE operation)

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Copyright 2004 Mani Srivastava

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Copyright 2004 Mani Srivastava

Design for Testability

M state regs (a) Combinational function (b) Sequential engine

Exhaustive test is impossible or unpractical

Copyright 2004 Mani Srivastava

Exhaustive testing has redundancy

same fault covered by many input patterns

Cost of detecting all patterns may not be worth it

typical test procedures attempt 95-99% coverage

Copyright 2004 Mani Srivastava

Ideal vs. Real Tests

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Copyright 2004 Mani Srivastava

Testing as Filter Process

Prob(pass test) = high

Mostly good chips

Fabricated chips Mostly bad chips

Defective chips Prob(bad) = 1- y

Prob(fail test) = high

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Copyright 2004 Mani Srivastava