Seminar on Memory systems

Topics
Memory maps
Memory access attributes
Bit-band operations
Pipeline
Cortex-M3 processor system block diagram
Memory system features

The cortex-m3 processor has different memory architecture from that of
traditional ARM processors

It has predefined memory map that specifies which bus interface is to be
used when a memory location is accessed .
Memory system in the cortex-m3 supports bit-band operation.
Cortex-m3 memory system also supports unaligned transfers and exclusive
accesses
Cortex-m3 supports both little endian and big endian.

Cortex-M3 predefined Memory Map
Memory maps
Cortex-M3 processor has fixed memory map. This makes it easier to port
software from one cortex-M3 product to another.
For Ex components such as nested vectored interrupt controller(NVIC)
And memory protection unit(MPU),have the same memory location in all
cortex-M3 products.
Some of the memory locations are allocated for private peripherals such as
debugging components. These debugging components include
Fetch patch and breakpoint unit(FPB)
Data watch-point and trace unit(DWT)
Instrumentation trace macro-cell(ITM)
Embedded trace macro-cell(ETM)
Trace port interface(TPIU)
ROM table


Cortex-M3 processor has a total of 4GB of address space

0.5-GB for code memory region.

program code can be located in the code region ,the SRAM region or the
external RAM region.
However , it is best to put the program code in the code region because
with this arrangements, the instruction fetches and data accesses are
carried out simultaneously on two separate bus interfaces.

0.5GB memory slot is allocated for SRAM Memory

The SRAM memory range is for connecting internal SRAM. Access to this
region is carried out via the system interface bus.
In this region, a 32-MB range is defined as a bit-band alias.
Within the 32bit-band memory range each word address
represents a single bit in the 1-MB bit-band region.


Another 0.5GB block of address range is allocated to on-chip peripherals.

Similar to the SRAM region , this region supports bit band alias and is
access via the system bus interface.
Instruction execution in this region not allowed.
The bit-band support in the peripheral region makes it easy to access
or change control and status bits of peripherals, making it easier to
program peripheral control.

Two slots of 1-GB memory space is allocated for external RAM and external
devices.
the difference between the two is that program execution in the
external device region is not allowed.





The last 0.5GB memory is for the system level components, internal
peripherals, external peripheral bus and vendor specific system peripherals.

there are 2 segments of the private peripheral buses(PPB)

Advanced high performance bus(AHB)PPB, for cortex-M3 internal AHB
peripherals only; this include NVIC,FPB,DWT,ITM
Advance peripheral bus (APB) PPB, for cortex-M3 internal APB devices
as well as external peripherals.


Memory access attributes

Bufferable: write to memory can be carried out by a write buffer while the
processor continues on next instruction execution .

Cacheable: data obtained from memory read can be copied to a memory
cache so that next time it is accessed the value can be obtained from the cache
to speed up the program.

Executable: the processor can fetch and execute program code from this
memory region.

Sharable: data in this memory region could be shared by multiple bus masters.


The memory access attributes for each memory region are as follows

Code memory region(0X00000000-0x1FFFFFFF):
this region is executable and the cache attribute is write-through(WT)
you can put data memory in this region as well.
if the data operations are carried out for this region , they will take place
via the data bus interface.
write transfers to this region are buffered.

SRAM memory region(0x20000000-0X3FFFFFFF):
this region is intended for on-chip RAM
write transfers to this region are non-cacheable, and each attribute is
write back ,write allocated(WB-WA).
this region is executable.

Peripheral region(0x40000000-0X5FFFFFFF):
this region is intended for peripherals.
the accesses are non-cacheable .
you cannot execute instruction code in this region.

External RAM region (0x60000000-0X9FFFFFFF):
this region is intended for either on-chip or off-chip memory.
The accesses are cacheable(WB-WA), and you can execute code in this
region.

External devices (0xA0000000-0XDFFFFFFF):
This region is intended for external devices and/or shared memory that
needs ordering/non-buffered accesses.
It is also a non-executable region

System region (0xE0000000-0XFFFFFFFF):
This region is for private peripherals and vendor-specific devices.
It is non-executable.
The accesses are strongly ordered(non-cacheable , non-bufferable.
BIT BAND OPERATIONS

Bit-band operation support allows a single load/store operation to access
(read/write) to a single data bit.
In the cortex-m3 this is supported in two predefined memory regions called bit
band regions.
1.Is located in the first 1mb of the SRAM region.
2.Is located in the first 1mb of the peripheral region.

These two memory regions can be accessed like normal memory , but they can
also be accessed via a separate memory region called the bit-band alias.



ex: to set bit 2 in word data in address 0X20000000, instead of using 3
instructions to read the data , set the bit and then write back the result , this
task can be carried out by a single instruction.
Assembler sequence for these two cases
bit-band support can simplify application if we need to read a bit in a
memory location.
Ex:if we need to determine bit 2 of address 0x20000000, we use these steps

Assembler sequences
Cortex-m3 uses the following terms for the bit band memory addresses

Bit-band region: this is a memory address region that supports bit-band
operation.
Bit-band alias: access to the bit-band alias will cause an access(a bit-band
operation)to the bit-band region.

There are two regions of memory for bit-band operations.
0x20000000-0x200FFFFF(SRAM,1MB)
0x40000000-0x400FFFFF(peripherals,1MB)

for the SRAM memory region,the remapping of the bit-band alias
is shown in table below
The bit-band region of the peripheral memory region can be accessed
via bit band aliased addresses
Advantages of bit-band operations

1. Used to implement serial data transfers in general-purpose
input/output(GPIO) ports to serial devices

2. The application code can be implemented easily because access to
serial data and clock signals can be separated.

3. Bit-band operations can also be used to simplify branch decisions.

Ex: if a branch should be carried out based on 1 single bit in a status
register in a peripheral,
instead of
Reading the whole register
Masking the unwanted bits
Comparing and branching

You can simplify the operations to
Reading the status bit via the bit-band alias(get 0 or 1)
Comparing and branching




4. Bit-band operation is atomic i.e., the read-modify-write sequence
cannot be interrupted by other bus activities.

5. Bit-band feature can be used for storing and handling boolean data in
the SRAM region.

ex: multiple boolean variables can be packed into one single memory
location to save memory space.


Data are lost when an
exception handler modifies a
shared memory location
Data loss prevention
with locked transfers
using the bit-band
feature.
Data are lost when a different
task modifies a shared
memory location.
Data loss prevention
with locked transfers
using the bit-band
feature.
The pipeline

The cortex-M3 has a three stage pipeline.
1.Instruction Fetch
2.Instruction Decode
3.Instruction execution

Disadvantage of normal pipelining

When running programs with mostly 16bit instructions , processor might not
fetch instructions in every cycle.

This is because the processor fetches up to two instructions(32 bit) in one go ,
so after one instruction is fetched , the next one is already inside the processor.
In this case , processor bus interface may try to fetch the instruction after the
next.

or if the buffer is full , the bus could be idle, some of the instructions take
multiple cycles to execute ; in this case , the pipeline will be stalled.
Inside the instruction pre-fetch unit of the processor core, there is also an
instruction buffer. this buffer allows additional instructions to be queued before
they are needed . this prevents the pipeline being stalled when the instruction
sequence contains 32-bit thumb instructions that are not word aligned.
A detailed block diagram of cortex-m3 processor

The Cortex-M3 processor contains not only the processor core but also a
number of components for system management, as well as debugging support
components.

These components are linked together using an Advanced High-Performance
Bus (AHB), and an Advanced Peripheral Bus (APB).

The Cortex-M3 processor is released as a processor subsystem. The CPU core
itself is closely coupled to the interrupt controller (NVIC) and various debug
logic blocks:

CM3Core:
The Cortex-M3 core contains the registers, ALU, data path, and bus
interface.

NVIC:
The NVIC is a built-in interrupt controller.
The number of interrupts is customized by chip manufacturers.
The NVIC is closely coupled to the CPU core and contains a number of
system control registers.
It supports the nested interrupt handling.


SYSTICK Timer:
The System Tick (SYSTICK) Timer is a basic countdown timer that can be
used to generate interrupts at regular time intervals, even when the system
is in sleep mode.
It makes OS porting between Cortex-M3 devices much easier because there
is no need to change the OSs system timer code.
The SYSTICK Timer is implemented as part of the NVIC.


WIC:
A module interface with NVIC but separated from the main processor
design to allow the system to wake up from interrupt events while the
processor (including the NVIC) is completely stopped or powered down.

MPU:
The MPU can be used to protect memory contents by, for example, making
memory regions read-only or preventing user applications from accessing
privileged applications data.

Bus Matrix:
A Bus Matrix is used as the heart of the Cortex-M3 internal bus system.
It is an AHB interconnection network, allowing transfer to take place on
different buses simultaneously unless both bus masters are trying to access
the same memory region.
The BusMatrix also provides additional data transfer management,
including a write buffer as well as bit-oriented operations (bit-band).
.

AHB to APB:
An AHB-to-APB bus bridge is used to connect a number of APB devices
such as debugging components to the private peripheral bus in the Cortex-
M3 processor.

SW-DP/SWJ-DP:
The Serial Wire Debug Port (SW-DP)/Serial Wire JTAG Debug Port (SWJ-DP)
work together with the AHB Access Port (AHB-AP) so that external
debuggers can generate AHB transfers to control debug activities.
There is no JTAG scan chain inside the processor core of the Cortex-M3;
most debugging functions are controlled by the NVIC registers through AHB
accesses.
SWJ-DP supports both the Serial Wire Protocol and the JTAG Protocol,
whereas SW-DP can support only the Serial Wire Protocol.


AHB-AP:
The AHB-AP provides access to the whole Cortex-M3 memory through a
few registers.
This block is controlled by the SW-DP/SWJ-DP through a generic debug
interface called the Debug Access Port (DAP).

ETM:
The ETM is an optional component for instruction trace, so some Cortex-M3
products might not have real-time instruction trace capability.
Trace information is output to the trace port through TPIU.
The ETM control registers are memory mapped, which can be controlled by
the debugger through the DAP.





DWT:
The DWT allows data watchpoints to be set up.
When a data address or data value match is found, the match hit event can
be used to generate watchpoint events to activate the debugger, generate
data trace information, or activate the ETM.

ITM:
The ITM can be used in several ways.
Software can write to this module directly to output information to TPIU, or
the DWT matching events can be used to generate data trace packets
through ITM for output into a trace data stream.

TPIU:
The TPIU is used to interface with external trace hardware such as trace
port analyzers.


FPB:
The FPB is used to provide Flash Patch and Breakpoint functionalities.
Flash Patch means that if an instruction access by the CPU matches a
certain address, the address can be remapped to a different location so that
a different value is fetched.

ROM table:
A small ROM table is provided.
This is simply a small lookup table to provide memory map information for
various system devices and debugging components.
Debugging systems use this table to locate the memory addresses of
debugging components.

Thank you