Internal and External memory

Memory Hierarchy is to obtain the highest possible access speed

while minimizing the total cost of the memory system
MEMORY HIERARCHY
Semiconductor Memory Types
Memory Type Category Erasure Write Mechanism Volatility
Random-access
memory (RAM)
Read-write memory Electrically, byte-level Electrically Volatile
Read-only
memory (ROM)
Read-only memory Not possible
Masks
Nonvolatile
Programmable
ROM (PROM)
Electrically
Erasable PROM
(EPROM)
Read-mostly memory
UV light, chip-level
Electrically Erasable
PROM (EEPROM)
Electrically, byte-level
Flash memory Electrically, block-level
Internal and External memory
Memory Cell Operation
6
Block Diagram of Memory
Example: 2MB memory, byte-addressable
N = 8 (because of byte-addressability)
K = 21 (1 word = 8-bit)
2
k
words
N-bit per word
Memory Unit
N-bit Data Input
(for Write)
N-bit Data Output
(for Read)
K-bit address
lines
Read/Write
Chip Enable
N
N
K
7
Memory Model
32-bit address space can address up to 4GB (2
32
)
different memory locations
Flat Memory Model
0x0A
0xB6
0x41
0xFC
Lower
Memory
Address

0x00000000
Higher
Memory
Address

0x00000001
0x00000002
0x00000003
0xFFFFFFFF 0x0D
8
Memory Description
Capacity of a memory is described as
# addresses x Word size
Examples:
Memory # of addr # of data lines # of addr lines # of total bytes
1M x 8 1,048,576 8 20 1 MB
2M x 4 2,097,152 4 21 1 MB
1K x 4 1024 4 10 512 B
4M x 32 4,194,304 32 22 16 MB
16K x 64 16,384 64 14 128 KB
Some basic concepts
Maximum size of the Main Memory
byte-addressable
CPU-Main Memory Connection

Up to 2
k
addressable
MDR
MAR
k -bit
address bus
n -bit
data bus
Control lines
( , MFC, etc.)
Processor
Memory
locations
Word length = n bits
W R /
10
MAR and MDR
Memory Address Register (MAR)
Contains Address in memory to find or
place data

Memory Data Register (MDR)
Contains Actual Data to be placed in
location given in MAR, or which has been
retrieved from location given in MAR
11
RAM: Random Access Memory
Random any piece of data can be accessed in a constant time
regardless of physical location (unlike tapes, magnetic or optical
discs)
Difference in technical design
DRAM (Dynamic RAM)
Most common, cheap
Volatile: must be refreshed (recharged with power) 1000s of times each
second
SRAM (static RAM)
Faster to access than DRAM and more expensive than DRAM
Volatile
small amount used in cache memory for high-speed access
12
RAM: Sample
DRAM modules used as primary memory in PCs, workstations, servers.
13
Static Random Access Memory (SRAM)
BitLine
BitLine
Wordline (WL)
Two transistor inverters are cross connected to implement a basic
flip-flop.
When word line is at ground level, the transistors are turned off
and the latch retains its state
Read operation: In order to read state of SRAM cell, the word line
is activated to close switches T1 and T2. Sense/Write circuits at
the bottom monitor the state of b and b
Stating RAM Structure
15
Dynamic Random Access Memory (DRAM)
1-transistor DRAM cell
During a write, put value on bitline and then set WL=1
Storage decays, thus requires periodic refreshing (read-sense-
write)
SRAM v DRAM
Both volatile
Power needed to preserve data
Dynamic cell
Simpler to build, smaller
More dense
Less expensive
Needs refresh
Larger memory units
Static
Faster
Cache

17
How to Address Memory
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
0
1
2
3
D7 D6 D5 D4 D3 D2 D1 D0
4x8 Memory
2-to-4

Decoder
A0
A1
CS
Chip
Select
Internal organization of memory chips
(Contd.,)
FF
circuit
Sense / Write
Address
decoder
FF
CS
cells
Memory
circuit
Sense / Write Sense / Write
circuit
Data input /output lines:
A
0
A
1
A
2
A
3
W
0
W
1
W
15
7 1
0
W R /
7
1 0
b
7
b
1
b
0

19
Building Memory in Hierarchy
Design a 1Mx8 using 1Mx4 memory chips
D3
D2
D1
D0
A19
A18
A17
A0
1Mx4
R/W CS
D7
D6
D5
D4
A19
A18
1Mx4
R/W CS
A17
A0
CS
20
Building Memory in Hierarchy
Design a 2Mx4 using 1Mx4 memory chips
A19
A18
A17
A0
1Mx4
R/W CS
A19
A18
A17
A0
1Mx4
R/W CS
A20
1-to-2
Decoder
CS
1
0
D3
D2
D1
D0
Note that 1-to-2
decoder is the wire
itself (or use
an inverter)
21
Memory controller (contd..)
Processor
R A S
C A S
R / W
Clock
Address
Row/Column
address
Memory
controller
R / W
Clock
Request
C S
Data
Memory
Simplified DRAM Read Timing