STATIC TIMING ANALYSIS

(STA)

Presenters:
N.Agni Teja
M.Sharan Kumar
K. Naveen Kumar


AGENDA
Intro to Timing Analysis(TA)
Paths and Delays
Setup and Hold Time
Example- if u can take it .?????

Note: Note down the def. in the presentation for
interview
What is Timing Analysis
In the asic flow anything can be
compromised but not TIMING !!!!!!!!!

Bcoz Time is Money !!!!! You pay for higher
clock speed, so you can work faster.

It is the process of estimating that the time
take for the digital circuit to perform the
intended task is as required or not !!!

WHERE TIMING COMES !!!!
Why TA ???
Whether we met the timing requirements or
not

Make sure.. that the circuit works in all
possible combinations over a set environment
at every TIME

Helps in components selection of your design
circuit.
Why STATIC TA
2 Types TA
STATIC TA
DYNAMIC- TA

Static Timing Analysis:
With out input/output vectors .
Dynamic Timing Analysis.
With input /output test vectors

Basics components of STA
1) CLOCK
All the parameters of the clock and parameters
effecting the clock should be understood
2) Seq. CKTS
The setup time and hold time concepts of the FF
and the parameters effecting it should be
understood.

BOTH ARE INTERLINKED



STA
Is a method of validating the timing performance

In all possible path in ckt under worst case condition

It check only for proper timing but not for proper
logical functionality.

Its FASTER and ACCURATE

It considers all the possible paths in the circuit
including the false path



Data path
There are 4 different ways to calculate data
path
Input pin/port to register
Input pin/port to output pin/port
Register to register
Register to output pin/port
DIFFERENT PATHS
Data paths
DIFFERENT PATHS
Clock path
Clock gating path
False path
No data is transferred from starting point to
ending point.
There may be a few paths in the design which
are not critical paths but masking other paths
which are important for timing optimization
then we have to declare them as the false
path.
False_path (directive)
Asynchronous path

The functionality of set/reset pin is
independent from the clock edge. Its level
triggered pins and can start functioning at any
time of data
DIFFERENT PATHS
FALSE PATH
DIFFERENT PATHS
MULTICYCLE PATH:
It is a timing path designed to make more than 1
clock cycle for the data to propagate from starting
to end point.
DIFFERENT PATHS
LAUNCH AND CAPTURE PATH

Launch path + data path = arrival time(data at the input of capture flip-flop
Capture clock period + path delay = required time(data at he input of capture register)
Delay
Majorly two types of delays

CELL DELAY

NET DELAY
Cell delay
Timing Delay between an input pin and an
output pin of a cell.
Cell delay information is contained in the
library of the cell.

TIMING ARC

Combinational arc
Sequential arc
NET DELAY
Net Delay refers to the total time needed to
charge or discharge all of the parasitic
(Capacitance / Resistance / Inductance) of a
given Net. So we can say that Net delay is a
function of
Net Resistance
Net Capacitance
Net Topology

DELAY
NET DELAY
RLC model
Wire Load model

Delay dependancy

SETUP AND HOLD TIME
Analogy of AIRPORT
SETUP TIME :Setup time is the minimum amount
of time the data signal should be held
steady before the clock event so that the data are
reliably sampled by the clock
HOLD TIME: Hold time is the minimum amount
of time the data signal should be held
steady after the clock event so that the data are
reliably sampled



There are only 2 conditions possible
1) Tpd DIN > Tpd Clk
Set up Time comes into play
2) Tpd DIN < Tpd Clk
Hold time comes into play
Tpd DIN (max) > Tpd Clk (min)
SetUp time == Tpd DIN (max) - Tpd Clk (min)
Tpd DIN (min) < Tpd Clk (max)
Hold time == Tpd Clk (max) - Tpd DIN (min)

Hold Analysis:
When a hold check is performed, we have to consider two things-
Minimum Delay along the data path.
Maximum Delay along the clock path.

Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D
Delay in Data path
= min(wire delay to the clock input of FF1) + min(Clk-to-Q delay of FF1) +min(cell delay of inverter) + min(2 wire delay- "Qof FF1-to-inverter" and
"inverter-to-D of FF2")
=Td = 1+9+6+(1+1)=18ns


Clock path is: CLK-> buffer -> FF2/CLK
Clock path Delay
= max(wire delay from CLK to Buffer input) + max(cell delay of Buffer) + max(wire delay from Buffer output to FF2/CLK pin) + (hold time of FF2)
=Tclk = 3+9+3+2 = 17 ns


Hold Slack = Td - Tclk = 18ns -17ns = 1ns

Setup Analysis:
When a setup check is performed, we have to consider two things-
Maximum Delay along the data path.
Minimum Delay along the clock path

Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D

Delay in Data path= max(wire delay to the clock input of FF1) + max(Clk-to-Q delay of FF1) +max(cell
delay of inverter) + max(2 wire delay- "Qof FF1-to-inverter" and "inverter-to-D of FF2")
=Td = 2+11+9+(2+2) = 26ns




Clock path is: CLK-> buffer -> FF2/CLK


Clock path Delay
= (Clock period) + min(wire delay from CLK to Buffer input) + min(cell delay of Buffer) + min(wire delay
from Buffer output to FF2/CLK pin) - (Setup time of FF2)
=Tclk = 15+2+5+2-4=20ns


Setup Slack = Tclk - Td = 20ns - 26ns = -6ns.

THANK YOU