Presented by:

Satish
Sandeep
Malvika Singh
Madhur Goel
Kuldeep Kumar

Coordinator:
Neerja Singh
(Asst. Prof.)
Contents:
Introduction
Conventional flash type ADC
TIQ based flash type ADC
TIQ comparator
Features of TIQ based ADC
Advantages of TIQ based flash type ADC
Technique used
DC Analysis
Transient Analysis
Observation
Future prospects .


Introduction
The flash ADC architecture has high speed conversion due
to its parallel structure.

Needs a large number of comparators as the resolution
increases.

A 3-bit flash ADC needs 7 comparators, but 63
comparators are needed for a 6-bit flash ADC.

This exponentially increasing number of comparator
requires a large die size and a large amount of power
consumption.

Conventional flash type ADC
TIQ based flash type ADC
The flash ADC features (TIQ) technique for high speed and low
power using standard CMOS technology.

The TIQ based flash ADC operates on power supply voltage of
0.7V.

The use of four cascading inverters as a voltage comparator is the
reason for the techniques name.

The voltage comparators compare the input voltage with internal
reference voltages. Which are determined by the transistor sizes of
the inverters.

Hence, resistor ladder circuit is not used.

TIQ Based Flash type ADC
TIQ Comparator
Vr
_
+
Vin
Vin Vin Vr Vth
Vout Vout
Vout Vin Vout Vth
DIFFERENTIAL INPUT
VOLTAGE COMPARATOR
INVERTER
Vr is provided by a voltage references source,
External to the voltage comparator
Vth is an internal parameter of an inverter,
fixed by the transistor sizes
Features of TIQ based ADC
Increased resolution

High Speed

Relatively small area

Relatively Low Power
Consumption


Advantages of TIQ based flash
type ADC
It eliminates the need of reference voltages which require
a resistor ladder circuit.

Here, threshold voltage of an inverter acts as reference
voltage.

Eliminates the need of high gain differential input voltage
comparators that are more complex and slower

Comparison operation speed is faster.

Techniques Used
In order to achieve minimum propagation delay:
Increase the sinking and sourcing current.
This can be achieved by :
Making the width of PMOS and NMOS large.
So in this work transistor sizing is used to achieve
minimum delay.
We used W/L >1

DC Analysis
V_V1
0V 50mV 100mV 150mV 200mV 250mV 300mV 350mV 400mV 450mV 500mV 550mV 600mV 650mV 700mV
V(M5:g) V(M4:d) V(M2:g)
0V
200mV
400mV
600mV
800mV
Transient Analysis
Time
0s 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns
V(M5:g) V(M4:d) V(M6:g)
0V
200mV
400mV
600mV
800mV
Observation
NMOS PMOS THRESHOLD VOLTAGE

W (nm) L (nm) W (nm) L (nm) (Vth)
100 90 95 90 0.99 V
100 90 120 90 1.01 V
100 90 170 90 1.012 V
NMOS PMOS Rise Time Fall Time Delay Time
W
(nm)
L
(nm)
W
(nm)
L
(nm)
(Tr)
(psec)
(Tf )
(psec)
(Td)
(nsec)
100 90 95 90 409.632 160.00129 0.19
100 90 120 90 6.40265 160.00311 0.18
100 90 170 90 6.40248 320.00244 0.15
DC ANALYSIS
TRANSIENT ANALYSIS
Formulae Used:
where, Wp = PMOS width,
Wn = NMOS width,
VDD =supply voltage,
Vtn = NMOS threshold voltage,
Vtp = PMOS threshold voltage,
n = electron mobility,
p = hole mobility.
PMOS length = NMOS
length(assumed).
where ==charge-carrier effective
mobility,
W=gate width,
L=gate length and
Cox=gate oxide capacitance per unit
area td=C Vdd/Id
Future Prospects
We will be using Logical Efforts a method to
determine minimum prop. delay prior to simulation
for cascaded inverters .
We will design the TIQ individual comparators in
particular (W/L>1) ratios.