AXI is an Interface Specification

Processor
Peripherals
PLB46
Arbiter
AXI Slaves
Interconnect
AXI AXI
AXI
AXI
AXI
Shared Access Bus
AXI Interconnect IP
Implementation is not
described in the spec
Several companies build and
sell AXI interconnect IP
Xilinx is building its own

Arrows indicate master/slave relationship,
not direction of dataflow
Master Slave
AXI
AXI
AXI
PLB
PLB
PLB
PLB
AXI is an interface
specification, not a bus
specification
AXI Masters
AXI
AXI
Advanced Microcontroller Bus Architecture
(AMBA)
AMBA
APB AHB AXI
AXI-4
Memory Map
AXI-4
Stream
AXI-4
Lite
ATB
AMBA 3.0
(2003)
AMBA 4.0
(Just Announced)
Same Spec
Enhancements for FPGAs
Interface Features Similar to
Memory Map /
Full
Traditional Address/Data Burst
(single address, multiple data)
PLBv46, PCI
Streaming Data-Only, Burst Local Link / DSP Interfaces
/ FIFO / FSL
Lite Traditional Address/DataNo Burst
(single address, single data)
PLBv46-single
OPB