Microcontroller 8051 - 1

• Section 1
Microprocessors course
Dr. S.O.Fatemi
By: Mahdi Hassanpour
Wednesday, November 25, 2009 Mahdi Hassanpour

Contents:
Introduction
Block Diagram and Pin Description of the 8051
Registers
Some Simple Instructions
Structure of Assembly language and Running
an 8051 program
Memory mapping in 8051
8051 Flag bits and the PSW register
Addressing Modes
16-bit, BCD and Signed Arithmetic in 8051
Stack in the 8051
LOOP and JUMP Instructions
CALL Instructions
I/O Port Programming

Introduction
General-purpose microprocessor
• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• Example ： Intel’s x86, Motorola’s 680x0
Many chips on mother’s board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus
General-Purpose Microprocessor System

Microcontroller :
• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example ： Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X
CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller

Microprocessor vs. Microcontroller
Microprocessor Microcontroller
• CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
• designer can decide on the • fix amount of on-chip ROM,
amount of ROM, RAM and RAM, I/O ports
I/O ports. • for applications in which cost,
• expansive power and space are critical
• versatility • single-purpose
• general-purpose

Embedded System
• Embedded system means the processor is embedded into that

application.
• An embedded product uses a microprocessor or microcontroller to
do one task only.
• In an embedded system, there is only one application software that
is typically burned into ROM.
• Example ： printer, keyboard, video game player

Three criteria in Choosing a Microcontroller
1. meeting the computing needs of the task efficiently and cost

effectively
• speed, the amount of ROM and RAM, the number of I/O ports
and timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
1. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator,
technical support
1. wide availability and reliable sources of the microcontrollers.

Block Diagram
External interrupts
On-chip Timer/Counter
Interrupt ROM for

On-chip Timer 1 Counter
Control program
RAM Timer 0 Inputs
code
CPU
Bus Serial
4 I/O Ports
OSC Control Port
P0 P1 P2 P3 TxD RxD
Address/Data

Comparison of the 8051 Family Members
Feature 8051 8052 8031

ROM (program space in bytes) 4K 8K 0K
RAM (bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6

Pin Description of the 8051
PDIP/Cerdip
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0
P1.2 3 38 P
) 0.1(AD1)
P1.3 4 8051 37 P0.2(AD2
P
P1.4 5 36 ) 0.3(AD3)
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14
(T1)P3.5 15 26 )P2.5(A13
(WR)P3.6 16 25 P
) 2.4(A12
(RD)P3.7 17 24 )P2.3(A11
XTAL2 18 23 P ) 2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8) 

Pins of 8051 （ 1/4 ）
• Vcc （ pin 40 ）：
– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
• GND （ pin 20 ）： ground
• XTAL1 and XTAL2 （ pins 19,18 ）：
– These 2 pins provide external clock.
– Way 1 ： using a quartz crystal oscillator 
– Way 2 ： using a TTL oscillator 
– Example 4-1 shows the relationship between XTAL and the
machine cycle. 

Pins of 8051 （ 2/4 ）
• RST （ pin 9 ）： reset

– It is an input pin and is active high （ normally low ） .
• The high pulse must be high at least 2 machine cycles.
– It is a power-on reset.
• Upon applying a high pulse to RST, the microcontroller will
reset and all values in registers will be lost.
• Reset values of some 8051 registers 
– Way 1 ： Power-on reset circuit 
– Way 2 ： Power-on reset with debounce 

Pins of 8051 （ 3/4 ）
• /EA （ pin 31 ）： external access

– There is no on-chip ROM in 8031 and 8032 .
– The /EA pin is connected to GND to indicate the code is stored
externally.
– /PSEN ＆ ALE are used for external ROM.
– For 8051, /EA pin is connected to Vcc.
– “/” means active low.
• /PSEN （ pin 29 ）： program store enable
– This is an output pin and is connected to the OE pin of the ROM.
– See Chapter 14.

Pins of 8051 （ 4/4 ）
• ALE （ pin 30 ）： address latch enable

– It is an output pin and is active high.
– 8051 port 0 provides both address and data.
– The ALE pin is used for de-multiplexing the address and data by
connecting to the G pin of the 74LS373 latch.
• I/O port pins
– The four ports P0, P1, P2, and P3.
– Each port uses 8 pins.
– All I/O pins are bi-directional.

Figure 4-2 (a). XTAL Connection to 8051
• Using a quartz crystal oscillator

• We can observe the frequency on the XTAL2 pin.
C2
XTAL2
30pF
C1
XTAL1
30pF
GND
Wednesday, November 25, 2009 Mahdi Hassanpour 

Figure 4-2 (b). XTAL Connection to an External Clock Source
N XTAL2
C
• Using a TTL oscillator
EXTERNAL
• XTAL2 is unconnected. OSCILLATOR
SIGNAL XTAL1
GND

Example :
Find the machine cycle for

(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz.
Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz;

machine cycle = 1 / 921.6 kHz = 1.085 µ s
(b) 16 MHz / 12 = 1.333 MHz;
machine cycle = 1 / 1.333 MHz = 0.75 µ s

RESET Value of Some 8051 Registers:
Register Reset Value

PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000
RAM are all zero.
Figure 4-3 (a). Power-On RESET Circuit
Vcc
10 uF 31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST

Figure 4-3 (b). Power-On RESET with Debounce
Vcc
31
EA/VPP
X1
10 uF 30 pF
X2
RST
9
8.2 K

Pins of I/O Port
• The 8051 has four I/O ports

– Port 0 （ pins 32-39 ）： P0 （ P0.0 ～ P0.7 ）
– Port 1 （ pins 1-8 ）： P1 （ P1.0 ～ P1.7 ）
– Port 2 （ pins 21-28 ）： P2 （ P2.0 ～ P2.7 ）
– Port 3 （ pins 10-17 ）： P3 （ P3.0 ～ P3.7 ）
– Each port has 8 pins.
• Named P0.X （ X=0,1,...,7 ） , P1.X, P2.X, P3.X
• Ex ： P0.0 is the bit 0 （ LSB ） of P0
• Ex ： P0.7 is the bit 7 （ MSB ） of P0
• These 8 bits form a byte.
• Each port can be used as input or output (bi-direction).

Registers
A
R0
DPTR DPH DPL
R1
R2 PC PC
R3
R4 Some 8051 16-bit Register
R5
R6
R7
Some 8-bitt Registers of

the 8051

Some Simple Instructions
MOV dest,source ; dest = source
MOV A,#72H ;A=72H

MOV A, #’r’ ;A=‘r’ OR 72H
MOV R4,#62H ;R4=62H
MOV B,0F9H ;B=the content of F9’th byte of RAM
MOV DPTR,#7634H
MOV DPL,#34H
MOV DPH,#76H
MOV P1,A ;mov A to port 1
Note 1:
MOV A,#72H ≠ MOV A,72H
After instruction “MOV A,72H ” the content of 72’th byte of RAM will replace in Accumulator.
8086 8051
MOV AL,72H MOV A,#72H
MOV AL,’r’ MOV A,#’r’
MOV BX,72H
MOV AL,[BX] MOV A,72H
Note 2:
MOV A,R3 ≡ MOV A,3

ADD A, Source ;A=A+SOURCE
ADD A,#6 ;A=A+6
ADD A,R6 ;A=A+R6
ADD A,6 ;A=A+[6] or A=A+R6
ADD A,0F3H ;A=A+[0F3H]

SETB bit ; bit=1
CLR bit ; bit=0
SETB C ; CY=1
SETB P0.0 ;bit 0 from port 0 =1
SETB P3.7 ;bit 7 from port 3 =1
SETB ACC.2 ;bit 2 from ACCUMULATOR =1
SETB 05 ;set high D5 of RAM loc. 20h
Note: Bit Addressable

Page 359,360
CLR instruction is as same as SETB
i.e:
CLR C ;CY=0
But following instruction is only for CLR:

CLR A ;A=0

SUBB A,source ;A=A-source-CY
SETB C ;CY=1
SUBB A,R5 ;A=A-R5-1
ADC A,source ;A=A+source+CY
SETB C ;CY=1
ADC A,R5 ;A=A+R5+1

DEC byte ;byte=byte-1
INC byte ;byte=byte+1
INC R7
DEC A
DEC 40H ; [40]=[40]-1
CPL A ;1’s complement

Example:
MOV A,#55H ;A=01010101 B
L01: CPL A
MOV P1,A
ACALL DELAY
SJMP L01 
CALL
NOP & RET & RETI
All are like 8086 instructions.

ANL - ORL - XRL
EXAMPLE:
MOV R5,#89H
ANL R5,#08H
RR – RL – RRC – RLC A
EXAMPLE:
RR A
Structure of Assembly language
and Running an 8051 program
EDITOR
PROGRAM
ORG 0H Myfile.asm
MOV R5,#25H ASSEMBLER
PROGRAM
MOV R7,#34H
Myfile.lst
MOV A,#0 Myfile.obj
Other obj file
ADD A,R5 LINKER

PROGRAM
ADD A,#12H
HERE: SJMP HERE Myfile.abs
END OH
PROGRAM
Myfile.hex
Memory mapping in 8051
• ROM memory map in 8051 family
4k 8k 32k
0000H 0000H 0000H
0FFFH
DS5000-32
1FFFH
8751
AT89C51
8752
AT89C52 7FFFH
from Atmel Corporation

from Dallas Semiconductor

• RAM memory space allocation in the 8051
7FH
Scratch pad RAM
30H
2FH
Bit-Addressable RAM
20H
1FH Register Bank 3
18H
17H
Register Bank 2
10H
0FH Stack) Register Bank 1)
08H
07H
Register Bank 0
00H

8051 Flag bits and the PSW register
• PSW Register
CY AC F0 RS1 RS0 OV -- P
Carry flag PSW.7 CY

Auxiliary carry flag PSW.6 AC
Available to the user for general purpose PSW.5 --
Register Bank selector bit 1 PSW.4 RS1
Register Bank selector bit 0 PSW.3 RS0
Overflow flag PSW.2 OV
User define bit PSW.1 --
Parity flag Set/Reset odd/even parity PSW.0 P
RS1 RS0 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH

Instructions that Affect Flag Bits:
Note: X can be 0 or 1

Example:
MOV A,#88H
ADD A,#93H
88 10001000
+93 +10010011
---- --------------
Example:
11B 00011011
MOV A,#9CH
CY=1 AC=0 P=0
ADD A,#64H
9C 10011100
Example: +64 +01100100
MOV A,#38H ---- --------------
ADD A,#2FH 100 00000000
CY=1 AC=1 P=0
38 00111000
+2F +00101111
---- --------------
67 01100111
CY=0 AC=1 P=1

Addressing Modes
• Immediate
• Register
• Direct
• Register Indirect
• Indexed

Immediate Addressing Mode
MOV A,#65H
MOV A,#’A’
MOV R6,#65H
MOV DPTR,#2343H
MOV P1,#65H
Example :
Num EQU 30
…
MOV R0,Num
MOV DPTR,#data1
…
ORG 100H
data1: db “IRAN”

Register Addressing Mode
MOV Rn, A ;n=0,..,7
ADD A, Rn
MOV DPL, R6
MOV DPTR, A
MOV Rm, Rn

Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct
addressing mode, it is most often used to access RAM loc. 30 – 7FH.
MOV R0, 40H

MOV 56H, A
MOV A, 4 ; ≡ MOV A, R4
MOV 6, 2 ; copy R2 to R6
; MOV R6,R2 is invalid !
SFR register and their address

Bit
MOV 0E0H, #66H ; ≡ MOV A,#66H Addressable
MOV 0F0H, R2 ; ≡ MOV B, R2 Page 359,360
MOV 80H,A ; ≡ MOV P1,A

Register Indirect Addressing Mode
• In this mode, register is used as a pointer to the data.
MOV A,@Ri ; move content of RAM loc.Where address is held by Ri into A

( i=0 or 1 )
MOV @R1,B
In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB
insructions.
Example:
Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM
location starting at 59h.
Solution:
MOV R0,37h ; source pointer
MOV R1,59h ; dest pointer
MOV R2,10 ; counter
L1: MOV A,@R0
MOV @R1,A
INC R0
INC R1
 jump
DJNZ R2,L1

Indexed Addressing Mode And On-Chip
ROM Access
• This mode is widely used in accessing data elements of
look-up table entries located in the program (code) space
ROM at the 8051
MOVC A,@A+DPTR
A= content of address A +DPTR from ROM
Note:
Because the data elements are stored in the program (code
) space ROM of the 8051, it uses the instruction MOVC
instead of MOV. The “C” means code.

• Example:
Assuming that ROM space starting at 250h contains “Hello.”, write a program to transfer the
bytes into RAM locations starting at 40h.
Solution:
ORG 0
MOV DPTR,#MYDATA
MOV R0,#40H
L1: CLR A
MOVC A,@A+DPTR
JZ L2
MOV @R0,A
INC DPTR
INC R0
SJMP L1
L2: SJMP L2
;-------------------------------------
ORG 250H
MYDATA: DB “Hello”,0
END
Notice the NULL character ,0, as end of string and how we use the JZ instruction to
detect that.

• Example:
Write a program to get the x value from P1 and send x2 to P2, continuously .
Solution:
ORG 0
MOV DPTR, #TAB1
MOV A,#0FFH
MOV P1,A
L01:
MOV A,P1
MOVC A,@A+DPTR
MOV P2,A
SJMP L01
;----------------------------------------------------
ORG 300H
TAB1: DB 0,1,4,9,16,25,36,49,64,81
END

16-bit, BCD and Signed
Arithmetic in 8051
Exercise:
 Write a program to add n 16-bit number. Get n

from port 1. And sent Sum to LCD
a) in hex
b) in decimal
 Write a program to subtract P1 from P0 and send

result to LCD
(Assume that “ACAL DISP” display A to LCD )
MUL & DIV
• MUL AB ;B|A = A*B
MOV A,#25H
MOV B,#65H
MUL AB ;25H*65H=0E99
;B=0EH, A=99H
• MUL AB ;A = A/B, B = A mod B
MOV A,#25
MOV B,#10
MUL AB ;A=2, B=5

Stack in the 8051
• The register used to access
7FH
the stack is called SP (stack
pointer) register. Scratch pad RAM
30H
• The stack pointer in the 2FH

Bit-Addressable RAM
8051 is only 8 bits wide,
which means that it can take 20H
1FH Register Bank 3
value 00 to FFH. When 18H
8051 powered up, the SP 17H
10H
Register Bank 2
register contains value 07. 0FH Stack) Register Bank 1)
08H
07H
Register Bank 0
00H

Example:
MOV R6,#25H
MOV R1,#12H
MOV R4,#0F3H
PUSH 6
PUSH 1
PUSH 4
0BH 0BH 0BH 0BH
0AH 0AH 0AH 0AH F3
09H 09H 09H 12 09H 12
08H 08H 25 08H 25 08H 25
Start SP=07H SP=08H SP=09H SP=08H

LOOP and JUMP Instructions
 DJNZ:
Write a program to clear ACC, then

add 3 to the accumulator ten time
Solution:
MOV A,#0;
MOV R2,#10
AGAIN: ADD A,#03
DJNZ R2,AGAING ;repeat until R2=0 (10 times)
MOV R5,A

• Other conditional jumps :
JZ Jump if A=0
JNZ Jump if A/=0
DJNZ Decrement and jump if A/=0
CJNE A,byte Jump if A/=byte
CJNE reg,#data Jump if byte/=#data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit

SJMP and LJMP:
LJMP(long jump)
LJMP is an unconditional jump. It is a 3-byte instruction in which
the first byte is the opcode, and the second and third bytes
represent the 16-bit address of the target location. The 20byte
target address allows a jump to any memory location from 0000
to FFFFH.
SJMP(short jump)
In this 2-byte instruction. The first byte is the opcode and the
second byte is the relative address of the target location. The
relative address range of 00-FFH is divided into forward and
backward jumps, that is , within -128 to +127 bytes of memory
relative to the address of the current PC.

CJNE , JNC
Exercise:
Write a program that compare R0,R1.

If R0>R1 then send 1 to port 2,
else if R0<R1 then send 0FFh to port 2,
else send 0 to port 2.

CALL Instructions
Another control transfer instruction is the CALL
instruction, which is used to call a subroutine.
• LCALL(long call)
In this 3-byte instruction, the first byte is the opcode
an the second and third bytes are used for the address
of target subroutine. Therefore, LCALL can be used
to call subroutines located anywhere within the 64K
byte address space of the 8051.

• ACALL (absolute call)
ACALL is 2-byte instruction in contrast to LCALL, which

is 13 bytes. Since ACALL is a 2-byte instruction, the target
address of the subroutine must be within 2K bytes address
because only 11 bits of the 2 bytes are used for the address.
There is no difference between ACALL and LCALL in
terms of saving the program counter on the stack or the
function of the RET instruction. The only difference is that
the target address for LCALL can be anywhere within the
64K byte address space of the 8051 while the target address
of ACALL must be within a 2K-byte range.

I/O Port Programming
Port 1 （ pins 1-8 ）

• Port 1 is denoted by P1.

– P1.0 ~ P1.7
• We use P1 as examples to show the operations on ports.
– P1 as an output port (i.e., write CPU data to the external pin)
– P1 as an input port (i.e., read pin data into CPU bus)

A Pin of Port 1
Read latch Vcc

TB2
Load(L1)
Internal CPU D Q P1.X

bus P1.X pin
Write to latch Clk Q M1
TB1
Read pin P0.x

8051 IC
Hardware Structure of I/O Pin
• Each pin of I/O ports
– Internal CPU bus ： communicate with CPU
– A D latch store the value of this pin
• D latch is controlled by “Write to latch”
– Write to latch ＝ 1 ： write data into the D latch
– 2 Tri-state buffer ：
• TB1: controlled by “Read pin”
– Read pin ＝ 1 ： really read the data present at the pin
• TB2: controlled by “Read latch”
– Read latch ＝ 1 ： read value from internal latch
– A transistor M1 gate
• Gate=0: open
• Gate=1: close

Tri-state Buffer
Output Input
Tri-state control
(active high)
L L H H Low
H H Highimpedance
(open-circuit)

Writing “1” to Output Pin P1.X
Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
D Q 1 P1.X
Internal CPU
bus P1.X pin
0 output 1
TB1
Read pin

8051 IC
Writing “0” to Output Pin P1.X
Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
D Q 0 P1.X
Internal CPU
bus P1.X pin
1 output 0
TB1
Read pin

8051 IC
Port 1 as Output （ Write to a Port ）
• Send data to Port 1 ：
MOV A,#55H
BACK: MOV P1,A
ACALL DELAY
CPL A
SJMP BACK
– Let P1 toggle.
– You can write to P1 directly.

Reading Input v.s. Port Latch
• When reading ports, there are two possibilities ：
– Read the status of the input pin. （ from external pin value ）
• MOV A, PX
• JNB P2.1, TARGET ; jump if P2.1 is not set
• JB P2.1, TARGET ; jump if P2.1 is set
• Figures C-11, C-12
– Read the internal latch of the output port.
• ANL P1, A ; P1 ← P1 AND A
• ORL P1, A ; P1 ← P1 OR A
• INC P1 ; increase P1
• Figure C-17
• Table C-6 Read-Modify-Write Instruction (or Table 8-5)
• See Section 8.3

Reading “High” at Input Pin
Read latch Vcc 2. MOV A,P1

TB2 external pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH
1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q
TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC
Reading “Low” at Input Pin
Read latch Vcc 2. MOV A,P1

TB2
1. write a 1 to the pin Load(L1) external pin=Low
MOV P1,#0FFH
1 0 P1.X pin
P1.X
0 M1
Write to latch Clk Q
TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC
Port 1 as Input （ Read from Port ）
• In order to make P1 an input, the port must be programmed by writing 1 to
all the bit.
MOV A,#0FFH ;A=11111111B

MOV P1,A ;make P1 an input port
BACK: MOV A,P1 ;get data from P0
MOV P2,A ;send data to P2
SJMP BACK
– To be an input port, P0, P1, P2 and P3 have similar methods.

Instructions For Reading an Input Port
• Following are instructions for reading external pins of ports:
Mnemonics Examples Description

MOV A,PX MOV A,P2 Bring into A the data at P2 pins
JNB PX.Y,.. JNB P2.1,TARGET Jump if pin P2.1 is low
JB PX.Y,.. JB P1.3,TARGET Jump if pin P1.3 is high
MOV C,PX.Y MOV C,P2.4 Copy status of pin P2.4 to CY

Reading Latch
• Exclusive-or the Port 1 ：
MOV P1,#55H ;P1=01010101
ORL P1,#0F0H ;P1=11110101
1. The read latch activates TB2 and bring the data from the Q latch into
CPU.
• Read P1.0=0
2. CPU performs an operation.
• This data is ORed with bit 1 of register A. Get 1.
3. The latch is modified.
• D latch of P1.0 has value 1.
4. The result is written to the external pin.
• External pin (pin 1: P1.0) has value 1.

Reading the Latch
1. Read pin=0 Read latch=1 Write to
latch=0 (Assume P1.X=0 initially)
Read latch Vcc

TB2
2. CPU compute P1.X OR 1 Load(L1)
0 4. P1.X=1
0 1 P1.X pin
1 P1.X
0
3. write result to latch Read
pin=0 Read latch=0
Write to latch=1
TB1
Read pin
8051 IC
Read-modify-write Feature
• Read-modify-write Instructions
– Table C-6
• This features combines 3 actions in a single instruction ：
1. CPU reads the latch of the port
2. CPU perform the operation
3. Modifying the latch
4. Writing to the pin
– Note that 8 pins of P1 work independently.

Port 1 as Input （ Read from latch ）
• Exclusive-or the Port 1 ：

MOV P1,#55H ;P1=01010101
AGAIN: XOR P1,#0FFH ;complement
ACALL DELAY
SJMP AGAIN
– Note that the XOR of 55H and FFH gives AAH.
– XOR of AAH and FFH gives 55H.
– The instruction read the data in the latch (not from the pin).
– The instruction result will put into the latch and the pin.

Read-Modify-Write Instructions
Mnemonics Example
ANL ANL P1,A

ORL ORL P1,A
XRL XRL P1,A
JBC PX.Y, TARGET JBC P1.1, TARGET
CPL CPL P1.2
INC INC P1
DEC DEC P1
DJNZ PX, TARGET DJNZ P1,TARGET
MOV PX.Y,C MOV P1.2,C
CLR PX.Y CLR P1.3
SETB PX.Y SETB P1.4

You are able to answer this Questions:
• How to write the data to a pin ？

• How to read the data from the pin ？
– Read the value present at the external pin.
• Why we need to set the pin first ？
– Read the value come from the latch （ not from the external
pin ） .
• Why the instruction is called read-modify write?

Other Pins
• P1, P2, and P3 have internal pull-up resisters.
– P1, P2, and P3 are not open drain.
• P0 has no internal pull-up resistors and does not connects to
Vcc inside the 8051.
– P0 is open drain.
– Compare the figures of P1.X and P0.X. 
• However, for a programmer, it is the same to program P0, P1,
P2 and P3.
• All the ports upon RESET are configured as output.

A Pin of Port 0
Read latch
TB2
Internal CPU D Q P0.X

bus P1.X pin
TB1
Read pin 
P1.x

8051 IC
Port 0 （ pins 32-39 ）
• P0 is an open drain.
– Open drain is a term used for MOS chips in the same way
that open collector is used for TTL chips. 
• When P0 is used for simple data I/O we must connect it to
external pull-up resistors.
– Each pin of P0 must be connected externally to a 10K ohm
pull-up resistor.
– With external pull-up resistors connected upon reset, port 0
is configured as an output port.

Port 0 with Pull-Up Resistors
Vcc
10 K
P0.0
DS5000 P0.1
Port 0
P0.2
8751 P0.3
8951 P0.4
P0.5
P0.6
P0.7

Dual Role of Port 0
• When connecting an 8051/8031 to an external memory, the 8051
uses ports to send addresses and read instructions.
– 8031 is capable of accessing 64K bytes of external memory.
– 16-bit address ： P0 provides both address A0-A7, P2 provides
address A8-A15.
– Also, P0 provides data lines D0-D7.
• When P0 is used for address/data multiplexing, it is connected to the
74LS373 to latch the address.
– There is no need for external pull-up resistors as shown in
Chapter 14.

74LS373
PSEN OE
ALE 74LS373 OC
G
P0.0 A0
D
P0.7 A7
D0
D7
EA
P2.0 A8
P2.7 A15
8051
Wednesday, November 25, 2009 Mahdi Hassanpour ROM
Reading ROM (1/2)
2. 74373 latches the
1. Send address to
PSEN address and send to
ROM OE
ALE ROM
G 74LS373 OC
P0.0 A0
D
P0.7 A7
Address
D0
D7
EA
P2.0 A8
P2.7 A12
8051 ROM
Reading ROM (2/2)
2. 74373 latches the
address and send to
PSEN ROM OE
ALE 74LS373 OC
G
P0.0 A0
D
P0.7 Address A7
D0
D7
EA 3. ROM send the
instruction back
P2.0 A8
P2.7 A12
8051
Wednesday, November 25, 2009 Mahdi Hassanpour ROM
ALE Pin
• The ALE pin is used for de-multiplexing the
address and data by connecting to the G pin of
the 74LS373 latch.
– When ALE=0, P0 provides data D0-D7.
– When ALE=1, P0 provides address A0-A7.
– The reason is to allow P0 to multiplex address and
data.

Port 2 （ pins 21-28 ）
• Port 2 does not need any pull-up resistors since
it already has pull-up resistors internally.
• In an 8031-based system, P2 are used to
provide address A8-A15.

Port 3 （ pins 10-17 ）
• Port 3 does not need any pull-up resistors since it already has
pull-up resistors internally.
• Although port 3 is configured as an output port upon reset, this
is not the way it is most commonly used.
• Port 3 has the additional function of providing signals.
– Serial communications signal ： RxD, TxD （ Chapter
10 ）
– External interrupt ： /INT0, /INT1 （ Chapter 11 ）
– Timer/counter ： T0, T1 （ Chapter 9 ）
– External memory accesses in 8031-based system ： /WR,
/RD （ Chapter 14 ）

Port 3 Alternate Functions
P3 Bit Function Pin
P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17 

INSTRUCTIONS:
Instruction are classified in to 5 categories.
1. Data transfer
2. Arithmetic
3. Logical
4. Boolean
5. Jump instructions.

1. Data transfer group of instructions.
• MOV
• MOVX
• MOVC
• PUSH and POP
• XCH

Immediate and register addressing mode
1. MOV A, #A
2. MOV A, Reg
3. MOV Reg , A
4. MOV Reg, # n
5. MOV DPTR, # nn
6. MOV Reg,Reg not allowed

Direct addressing mode.
1. MOV A, add
2. MOV add, n
3. MOV REG, add
4. MOV add, reg
5. MOV add , #n
6. MOV add1 , add2 (used to move from reg to
reg)

• Indirect addressing mode
• Data access from external memory.
• MOVX A, @ RP MOVX to move from
• MOVX A@DPTR external RAM
• MOVX @ RP, A
• MOVX @ DPTR, A
• MOVC A, @A+DPTR MOVC to get data from
• MOVC A, @A+PC external ROM

PUSH address
Pop address
DATA Exchange
1. XCH A, Rr all modes except immediate
2. XCH A, add may be used in exchange
3. XCH A, @RP must always involve A
4. XCH A, @RP
5. XCHD A,@RP exchanges lower nibbles

• Arithmetic group of Instructions
Increment and decrement instructions
1. INC A
2. INC Rr
3. INC add
4. INC @ Rp
5. INC DPTR DEC DPTR not allowed

• Add A, #n Addc A, #n
• Add A, Rr Addc A, Rr
• Add A, add Addc A, add
• Add A, @Rp Addc A, @Rp
Subtract with borrow

1. SUBB A, #n
2. SUBB A, Rr
3. SUBB A, add
4. SUBB A, @Rp

Subtract with borrow
1. SUBB A, #n
2. SUBB A, Rr
3. SUBB A, add
4. SUBB A, @Rp

Multiplication
MUL AB
BA (A)*(B)
lower byte
Higher byte
Flags affected
Cy is cleared, ov affected depending on the
result in 8 register.

DIVISION:
DIV AB
Reg A unsigned
Reg B
After division, Integer - quotient A
Integer - remainder B
Cy is cleared, AC is unaffected and even
OV is affected – SET TO 0 – DIV BY 0.

Logical group of Instructions.
AND
ANL A, #n
ANL A, Rr
ANL A, add
ANL A, @Rp
ANL addr, A
ANL add #n

OR XOR
ORL A, #n XRL A, #n
ORL A, Rr XRL A, Rr
ORL A, add XRL A, add
ORL A, @Rp XRL A, @Rp
ORL addr, A XRL add, A
ORL add, #n XRL add, #n

Rotate always with respect to ACC
RL A Rotate left acc
RLC A Rotate left acc with carry
RR A
RRC A
SWAP A Lower nibble and higher nibbles are
exchanged
CLR A clears A
CPL A Compliment

Branch group of instructions
Jump and call
1. Jump unconditionally
2. Decrement byte and jump if not equal
3. Compare bytes and jump if not equal
4. Jump on bit conditions
5. Call a subroutine and return from
subroutine

Unconditional jump:
It can be of 3 ranges
-Relative range – SJMP radd – 2 byte instn
-Absolute range
AJMP radd jump to any where within a
2 byte instruction page

address is 11 bit
-long range
LJMP Ladd 3 byte

JMP @ A + DPTR indirect jump
Jump to the address which is obtained by adding
A+ DPTR.
Flags are not affected in any these instructions.
Byte Jumps
All byte jumps are relative to pc.
DJNZ Rn, radd
DJNZ add, radd decrement contents of
memory.
Decrement and then jump.
None of the flags are affected.( No zero flag)

CJNE A , add , radd
CJNE A, #N , radd
CJNE Rn, #n , radd
CJNE @ Rp, #n , radd
BIT jumps
All bit jumps are relative to pc
JC add jump on carry
JNC add jump on no carry.
JB b, add b- address bit, jump if
addressed bit is set to 2
JNB b, add jump if address bit reset.

JBC b, add jump to relative addr if
addressed bit is set to one and clear
the addressed bit
JZ radd wrt acc
JNZ radd

Microcontroller 8051 - 1

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• Section 1

By: Mahdi Hassanpour

Wednesday, November 25, 2009 Mahdi Hassanpour

Wednesday, November 25, 2009 Mahdi Hassanpour

Many chips on mother’s board

General-Purpose Microprocessor System

Wednesday, November 25, 2009 Mahdi Hassanpour

CPU RAM ROM

Wednesday, November 25, 2009 Mahdi Hassanpour

Wednesday, November 25, 2009 Mahdi Hassanpour

• Embedded system means the processor is embedded into that

Wednesday, November 25, 2009 Mahdi Hassanpour

1. meeting the computing needs of the task efficiently and cost

Wednesday, November 25, 2009 Mahdi Hassanpour

Interrupt ROM for

Wednesday, November 25, 2009 Mahdi Hassanpour

Feature 8051 8052 8031

Wednesday, November 25, 2009 Mahdi Hassanpour

Wednesday, November 25, 2009 Mahdi Hassanpour

Wednesday, November 25, 2009 Mahdi Hassanpour

• RST （ pin 9 ）： reset

Wednesday, November 25, 2009 Mahdi Hassanpour

• /EA （ pin 31 ）： external access

Wednesday, November 25, 2009 Mahdi Hassanpour

• ALE （ pin 30 ）： address latch enable

Wednesday, November 25, 2009 Mahdi Hassanpour

• Using a quartz crystal oscillator

Wednesday, November 25, 2009 Mahdi Hassanpour 

Wednesday, November 25, 2009 Mahdi Hassanpour 

Find the machine cycle for

(a) 11.0592 MHz / 12 = 921.6 kHz;

Wednesday, November 25, 2009 Mahdi Hassanpour 

Register Reset Value

Wednesday, November 25, 2009 Mahdi Hassanpour 

Wednesday, November 25, 2009 Mahdi Hassanpour 

• The 8051 has four I/O ports

R4 Some 8051 16-bit Register

Some 8-bitt Registers of

Wednesday, November 25, 2009 Mahdi Hassanpour

MOV A,#72H ;A=72H

MOV P1,A ;mov A to port 1

Wednesday, November 25, 2009 Mahdi Hassanpour

ADD A,#6 ;A=A+6

ADD A,R6 ;A=A+R6

ADD A,6 ;A=A+[6] or A=A+R6

ADD A,0F3H ;A=A+[0F3H]

Wednesday, November 25, 2009 Mahdi Hassanpour

Note: Bit Addressable

But following instruction is only for CLR:

Wednesday, November 25, 2009 Mahdi Hassanpour

ADC A,source ;A=A+source+CY

Wednesday, November 25, 2009 Mahdi Hassanpour

CPL A ;1’s complement

All are like 8086 instructions.

Wednesday, November 25, 2009 Mahdi Hassanpour

ADD A,R5 LINKER

• ROM memory map in 8051 family

from Atmel Corporation

Wednesday, November 25, 2009 Mahdi Hassanpour

Scratch pad RAM

Wednesday, November 25, 2009 Mahdi Hassanpour

Carry flag PSW.7 CY