DIGITAL VLSI DESIGN

Abhinav Vishnoi
Assistant Professor
Lovely Professional University
COURSE SYLLABUS
1. Review of digital design :
MUX based digital design, Programmable Logic Arrays
(PLA) and Programmable Array Logic (PAL), Sequential
circuits and timing, Design of a pattern sequence
detector using MUX, Design of a vending machine
controller using PAL, Sequential circuit design (Moore
and Mealy circuits)

2. Introduction to Verilog coding :
Introduction to Verilog, Realization of combinational
and sequential circuits, RTL coding guidelines, Coding
organization and writing a test bench, Design flow


3. Design using algorithmic state machine
charts :
Derivation of ASM charts, Design examples
such as dice game etc using ASM charts,
Implementation of ASM charts using
microprogramming, Verilog design of bus
arbitrator


AFTER MTE
4.
(i) Design of memories :
Verilog realization of Read Only Memory (ROM),
Verilog realization of Random Access Memory
(RAM), Verilog coding of controller for accessing
external memory

(ii) Design of arithmetic functions :
Pipelining concept, Verilog design of a pipelined
adder/subtractor, Design of multipliers, Verilog
design of a pipelined multiplier

5. Design for testability :
Design for testability, Testing combinational and
sequential logic, Boundary scan testing and
Built-in self test

6. Introduction to FPGA :
Configurable logic block (CLB), Introduction to
Xilinx series, FPGA, FPGA based design using
Verilog



TEXT AND REFERENCE BOOKS
Text Book
1.Digital Integrated Circuits: A Design
Perspective by J. Rabaey, Prentice Hall of
India, 2nd Edition, (1997)
Reference Books
1.Verilog HDL by Samir Palnitkar, , Pearson
Education Publications, 2nd Edition, (2013)
2. Digital design by Morris mano, Prentice Hall
of India, 5th Edition, (2001)


WHAT DO YOU MEAN BY
VLSI DESIGN?
VLSI:VERY LARGE SCALE INTEGRATION
Integration: Integrated Circuits
multiple devices on one substrate
How large is Very Large?
SSI (small scale integration)
7400 series, 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1,000-10,000 transistors
VLSI > 10,000 transistors
ULSI

Integration Improves the Design
Lower parasitics, higher clocking speed
Lower power
Physically small

Integration Reduces Manufacturing Costs
(almost) no manual assembly
About $1-5billion/fab
Packaging is largest cost
Testing is second largest cost

Need of VLSI

Specifications
IO, Goals and Objectives, Function,
Costs

Architectural Description
VLHD, Verilog, Behavioral, Large
Blocks

Logic Design
Gates plus Registers

Circuit Design
Transistors sized for power and speed
Discrete Logic, Technology Mapping

Layout
Size, Interconnect, Parasitics
Levels of Design