1: Background 1

Alpha Breathing
Breath in

Breath out

Hold
1: Background 3
Memory
The same as that previously described for SIC.
Maximum memory available on a SIC/XE system is
1MB.
Registers
The SIC/XE machine architecture
1: Background 4
Data formats (48-bit floating point)
f*2^(e-1024)

Instruction formats and addressing modes
e=0 means Format 3 ; e=1 means Format 4
i=0, n=0 means SIC machine (for upward compatible)
i=1, n=0 means immediate addressing
i=0, n=1 means indirect addressing
i=1, n=1 means simple addressing




The SIC/XE machine architecture (cont.)
1: Background 5
1: Background 6
1: Background 7
Instruction set
SIC/XE provides all of the instructions that are available on
the standard versions.
It also provides instructions to perform floating-point
arithmetic operations (ADDF, SUBF, MULF, DIVF..)
Register-to-register arithmetic operations (ADDR,
SUBR,)
Input and Output
SIO (start I/O channel), TIO (test I/O channel) and HIO (halt
I/O channel)




The SIC/XE machine architecture (cont.)
1: Background 8
Data movement


The SIC/XE programming examples
1: Background 9
Data movement


Compared the SIC with SIC/XE
1: Background 10
Arithmetic operations


The SIC/XE programming examples (cont.)
1: Background 11
Looping and indexing operations


The SIC/XE programming examples (cont.)
MOVECH
STR1
STR2
1: Background 12
Indexing and looping operations


The SIC/XE programming examples (cont.)
1: Background 13
Subroutine call and record input operations


The SIC/XE programming examples (cont.)
1: Background 14
CISC: Complex Instruction Set Computers machine.
relatively large and complicated instruction set.
several different instruction formats and length
many different addressing modes.

E.g., VAX, Pentium

The implementation of such an architecture in
hardware tends to be complex.
CISC vs. RISC
1: Background 15
Introduced by Digital Equipment Corporation
(DEC) in 1978.
Memory
All addresses used are byte addresses.
2 bytes forms a word, 4 bytes forms a longword
8 bytes forms a quadword, 16 bytes forms a octaword
Registers
16 general-purpose register. (R15: program counter,
R14: stack pointer, R13: frame pointer, R12: argument
pointer)

The VAX architecture (CISC)
1: Background 16
RISC: Reduced Instruction Set Computers machine
Standard, fixed instruction length
Single-cycle execution of most instructions
Relatively large number of general-purpose registers
Relatively small number of machine instructions
Relatively small number of instruction formats and
addressing modes.

E.g., UltraSPARC, PowerPC, Cray T3E

The implementation of such an architecture in
hardware tends to be simple.

CISC vs. RISC
1: Background 17
Introduced by Sun Microsystem in 1995.
Memory
All addresses used are byte addresses.
2 bytes forms a halfword, 4 bytes forms a word
Registers
A large register file (more than 100 general-purpose
register)
Fixed instruction length

The UltraSPARC architecture (RISC)