A Seminar Report on

SPINTRONICS
DEPARTMENT OF ELECTRONICS
AND
ELECTRICAL COMMUNICATION
ENGINEERING,
IITKGP

GUIDED BY :PROF. T.K .BHATTACHARYA
PROF. P.CHAKKRABORTY

PRESENTED BY:BISHWAJEET KUMAR
10EC62R06


Contents
Abstract
The Logic of Spin
Need of New technology
Spin Wire
The Landauer-Shannon limit
Problem of Directionality and its solution
Spin Devices
Spin MUX
Spin Adders
Universal Toffoli gate using Spin
Conclusion
References
ABSTRACT


Spin of electron has been identied as a new state
variable that should be explored as an alternative to the
electrons charge for use beyond CMOS .
The use of pure spin currents to process information is
attractive because it potentially circumvents the
constraints of capacitive time constants, resistive power
dissipation, and heat buildup which accompany charge
motion.
These advances in spin era raise hopes for a brand new
digital electronics technology predicated on the use of the
spin degree of freedom of an electron, in lieu of the
charge degree of freedom, to store, process, and transmit
digital information

The Logic of Spin

Spin is a purely quantum phenomenon roughly akin to the
spinning of a childs top or the directional behaviour of a
compass needle.
The top could spin in the clockwise or counter-clockwise
direction; electrons have spin of a sort in which their compass
needles can point either up or down in relation to a
magnetic field.
Spin therefore lends itself legantly to a new kind of binary
logic of ones and zeros.
The movement of spin, like the flow of charge, can also carry
information among devices. One advantage of spin over
charge is that spin can be easily manipulated by externally
applied magnetic fields, a property already in use in magnetic
storage technology.
One device already in use is the giant
magnetoresistive(GMR)
Need of new technology

Power related issues
If the energy dissipation per bit flip does not decrease
considerably and still hovers around ~1 fJ, while at the same
time the clock frequency creeps up to 10GHz, then the power
dissipated per bit flip goes up to 10 mW. Now, with a
transistor density of 10
13
cm
-2
, the resultant power dissipation
per unit area will be 100 MW/cm
2
, which exceeds that in a
rocket nozzle! There is no on-chip heat sinking technology on
the horizon that can even dream of coping with that.
So, we are moving inexorably towards chip meltdown. The
International Technology Roadmap for Semiconductors has
termed this catastrophe the Red Brick Wall that cannot be
crossed, unless we can drastically reduce the energy
dissipation during bit flip.
Eliminating QV loss
By placing a single electron in a magneticfield, we can make
its spin polarization bistable since only polarizations parallel
and antiparallel to the field are stable (or metastable).
These two polarizations could represent logic bits 0 and 1.
Switching between them would require simply flipping an
electrons spin, without physically moving the electron in
space and causing current flow.
This eliminates the QV dissipation since we are not
changing the magnitude of charge in a given region of space
( QV= 0) .Since no current (I) flows, there is no I
2
R
dissipation in any external circuit (R is the resistance in the
circuit).Encoding logic bits in spin polarization can therefore
spawn extremely energy efficient logic devices that dissipate
very little energy when the bit switches.

Spintronic realization of a single NAND gate.

The spin configurations when(a)both inputs are logic1 (upspin),(b) both
inputs are logic0 (downspin),(c)and(d) one input is logic1 and the other is
logic0. [1]

. Ref: H. Agarwal, S. Pramanik, and S. Bandyopadhyay,
Single spin universal Boolean logic gate, New J. Phys., vol. 10, p. 015001, 2008.
Truth tableof a spintronic NANDgate
Input1 Input2 Output
1 1 0
1 0 1
0 1 1
0 0 1

Spin Wire
Spin wire
Ref : Marc Cahay and SupriyoBandyopadhyay,
An electrons spin , IEEE POTENTIALS 2009
A spin-wire is a linear array of quantum dots
each containing a single electron that interacts
with its nearest neighbours via exchange.
The spin state in any dot can be dynamically
transferred to every alternate dot by sequentially
clocking the dots pair wise using a three-phase
clock. This allows unidirectional propagation of
spin bits down the chain, which then mimics a
spin-wire.
To achieve this in practice, a gate pad is
inserted between each pair of dots. When the
electrostatic potential applied to a pad is zero,
the potential barrier between the two flanking
dots is so high that the exchange coupling
between them is negligible.
When a positive potential is applied to a gate
pad, the barrier is lowered and the two
electrons on either side are exchange coupled.
When this act is carried out by raising the
potentials of two succeeding gate pads
simultaneously, three consecutive electrons
are exchange coupled (nearest neighbour
only) and the third electron begins to assume
the polarization of the first as the array
approaches the ground state
Agarwal and his coworkers also showed that the
energy dissipated in switching the NAND gate is
kTln(1/p) , where k is Boltzmanns constant, T the
temperature in Kelvin, and p is the gate error
probability associated with the gate straying from
the ground state to an excited state.
The probability of occupying an excited state (and
hence the gate error probability) can be made very
small in quantum dot systemsas small as ~10
10

,if we work at very low temperatures (~1 K).
With an error probability of 10
10
, the energy
dissipated per bit flip is kT ln(10
10
) =23 kT, which is
~3 x 10
22
Joules for T=1K. Even with a 10 GHz
clock, the power dissipated per bit flip will now be
only ~3 picoWatts. If the gate density is 10
13
cm
2
,
the power dissipated per unit area will be a modest
30 W/cm2, which is easily handled with todays
technology.
The Landauer-Shannon limit
No irreversible logic device that is in equilibrium with its
surroundings can dissipate anything less than kTln(1/p) amount of
energy,regardless of what it is made and its level of sophistication.
This limitis fundamental and technology-independent.It is now
called the Landauer-Shannon limit after Rolf Landauer and Claude
Shannon, who also contributedto this idea.
The only way to beat it is to use a device that is not in equilibrium
with its surroundings.
Spin can be a very attractive alternate state variable to ultimately
beat the Landauer-Shannon limit. That is because spin couples very
weakly to its surroundings and therefore can be retained out of
equilibrium for a long time. A result of the weak coupling is that spin
relaxes very slowly when it is coupled to its surroundings.
Lack of Unidirectionality
The real problem is exchange interaction is
bidirectional which cannot ensure
unidirectional flow of logic signal from the input
to the output of the logic device.
This unidirectionality is a required attribute of
any logic device.
Possible solution
A more elegant solution is inspired by the
realization that in charge coupled device
(CCD) arrays, there is no inherent
unidirectionality, yet charge is made to
propagate from one device to the next
unidirectionally. This is achieved by clocking
Thus by lowering two adjacent barriers
pairwise at the same time, we can propagate
the input state through a linear array. In other
words, we will need a three-phase clock,a
single phase will not work.
Ref :H. Agarwal, S. Pramanik, and S. Bandyopadhyay,
Single spin universal Boolean logic gate, New J. Phys., vol. 10, p. 015001, 2008.
Fig.(a)Three conventional inverters in series with the logic
states at four different nodes(A,B,CandD) shown,
(b)spintronic realization of the circuit in Fig.(a),(c) the spin
states at time t=0+, immediately after the leftmost spin is
flipped by an external input,
(d)configurations attainable with3-phase clocking,
(e)when first two gates are raised in potential
(f)when the next two gates are raised in potential
(g)the three clockpulse trains required in this case are shown.
The first gate is tied to the first train, the second to the
second train and the third to the third train.Then the fourth
gate is again tied to the first train and the pattern
repeated.The period between t1 and t2 corresponds to Fig.(e)
and the period between t2 andt3 corresponds to Fig.(f).

SPIN DEVICES
Multiplexer using Single Spin

2:1 MUX
Ref : T.K.Bhattacharya et.al. , single spin implementation
of a multiplexer,Physica E 41 (2009) 1184-1186.

The circles in Fig. denote quantum dots where an electron
is trapped, and the arrow denotes the spin polarization of
that electron in the presence of an external magnetic eld
that denes the two directions for the bistable spin
polarization vector.
The spins may be aligned along or against the external eld
using local magnetic elds before the structure is set into
action.
The S input controls the potential barrier of the two gate pads
separating the central dot from the other two. When S= 0, the
barrier remains high, effectively decoupling the two
electrons. When S = 1, the barrier is reduced, and the
electrons in the two dots separated by that gate pad are
exchange coupled.

Truth table of 2:1 MUX
Using A and B as the initial alignment of the spin polarization in the two dots,
and following the convention that the output be quoted opposite to the
observed spin polarization in the output dot, the truth table is obtained for
the steady-state spin polarizations of the system
4:1 MUX

4:1 MUX
Ref : T.K.Bhattacharya et.al. , single spin implementation
of a multiplexer,Physica E 41 (2009) 1184-1186.

First a selection is made between A and B to
determine X and C and D to determine Y using
least signicant control bit S0, and then between
X and Y to determine output bit based on
most signicant bit S1.
The Isolators marked are essentially similar to
the gate pads, except that they are permanently
high-potential barriers that prevent unwanted
exchange coupling between the electrons housed
in unwanted exchange coupling between the
electrons housed in different dots of the system.

Spintronic adder
Circuit to find S
Ref : A.Sarkar et al. , A nonmagnetic spintronicadder,
Journal of Applied Physics 101,036108(2007).

The two bits are encoded in the spin of the
incoming electron (b2) and the gate voltage (b1).
The up-spin state is assumed to be 0 and the
down-spin state is assumed to be 1.
The gate voltage has two states V(1) and V(0).
Only when the voltage is V(1), the spin state is
flipped owing to Rashba interaction. Thus a CNOT
gate is implemented.
The sum output is obtained by spin readout. This
spin readout can be done by a downspin detector,
which gives a nonzero output only when a
downspin is present at the nanowire output.

Carry scheme I :Intertwined nanowire
based carry circuit
Ref : A.Sarkar et al. , A nonmagnetic spintronicadder,
Journal of Applied Physics 101,036108(2007).

In this case the bits are encoded in the mode
of the nanowire and the spin of the electron.
The up-spin (0) electron is released in the 1
mode or the down-spin (1) electron is
released in the 0 mode.
The down-spin detector produces a nonzero
output (output 1) only when a down-spin
electron (spin 1) is released in the 1 mode
at the input. In essence we have achieved an
AND gate which serves the purpose of the
carry circuit.
Carry scheme II
Ref : A.Sarkar et al. , A nonmagnetic spintronicadder,
Journal of Applied Physics 101,036108(2007).

In this scheme, one of the bits is encoded in the
spin of the electron as earlier. Another bit is
encoded in the control voltage of the down-spin
filter.
When the control voltage is high [V(1)], the filter
passes down-spin (spin 1)electrons; when the
control voltage is low (0) the electrons are
blocked.
Thus it is evident that the electron detector
detects electrons only when a down-spin electron
is available at the input and the control voltage of
the spin filter is 1. Hence, an AND gate is
realized and the carry circuit is implemented
Universal Toffoli gate
Truth table of Toffoli gate
Schematic of the implementation of
theToffoligate
Ref : T.K.Bhattacharya et.al, Universal Toffoli gate in ballistic
nanowires,Applied Physics Letters 90,173101(2007)

CONCLUSION
Spin logic can be used for computations.
Power handling problems can be better solved by using spin
technique.
Spin can be used to make digital logic gates like MUX ,Adders etc. .
Spin can be harnessed for creating a new generation of classical
computers that could be extraordinarily energy- efficient.
Still persist the challenges of creating and measuringspin,
understanding better thetransport of spin at interfaces, particularly
at semiconductor
interfaces, and clarifying the types oferrors in spin-based
computational
systems.
Also theoretical understanding of quantumspin, learning in the
process how to activelycontrol and manipulate spins inultrasmall
structures is required.

References

1. H. Agarwal, S. Pramanik, and S. Bandyopadhyay, Single spin universal Boolean logic gate, New J.
Phys., vol. 10, p. 015001, 2008.


2. Marc Cahay and SupriyoBandyopadhyay, An electrons spin , IEEE POTENTIALS 2009

3.T.K.Bhattacharya et.al. , single spin implementation of a multiplexer,Physica E 41 (2009) 1184-1186.

4. A.Sarkar et al. , A nonmagnetic spintronicadder,Journal of Applied Physics 101,036108(2007).

5. T.K.Bhattacharya et.al, Universal Toffoli gate in ballistic nanowires,Applied Physics Letters
90,173101(2007)

6. S.Datta and B.Das,Applied Physics letter 56,665(1990)

7. Materials Today, Volume 6, Issue 5, May 2003.

8. Das Sarma, S., et al. 2001. Spin electronics and spin computation. Solid State Communications 119:207.

9.Wikipedia.org

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