Sunteți pe pagina 1din 121

Figure 2.1 Circuit symbol for the op amp.

Op Amps
Op Amps are Operational Amplifiers
Simple, standardized conceptual amplifier which you can buy for pennies
Wide range of specifications and specialties
Low cost, precision, fast, low power, high voltage, high impedance,
high current drive, multiple inputs, differential, etc. etc.
Manufacturers may sell hundreds of versions in multiple packages
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Op Amps versatile to work withcan do a wide variety of tasks
Feedback makes op amps reliable, manufacturable

Op amps considered here have three terminals
Inverting input
Noninverting input
Output
Dont forget op amps actually must have power connections, usually two in
this chapter
V
CC
positive supply
V
EE
negative supply
May have other inputs like clock signals, frequency compensation, offset
correction, etc.


Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Inverting input
Noninverting input
Output
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Inverting input
Noninverting input
Output
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Inverting input
Noninverting input
Output
Remember, V
CC
and V
EE
need to be connected to ground for real in the
Lab or in simulation!
Ground will be the circuit common nodeall signals referenced
to ground
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Inverting input
Noninverting input
Output
Whats the minimum number of terminals required for a single op amp?
Whats the minimum number of terminals required an op amp in a
package containing two op amps?
D
D
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Inverting input
Noninverting input
Output
Whats the minimum number of terminals required for a single op amp
IC? 3+2=5
Whats the minimum number of terminals required an op amp in an IC
package containing two op amps?
-- 3+3+2=8
(power and ground internally routed)
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.3 Equivalent circuit of the ideal op amp.
Op Amps
Op amps sense the difference between the inputs and amplifies
that difference, everything is referenced to the circuit ground
We should write
Inverting input=v
1
-ground=v
1
-0
Noninverting input=v
2
-ground=v
2
-0

These voltage differences appear at
the output amplified by the gain A

(v
3
-0)=A[(v
2
-0)-(v
1
-0)]
h
t
t
p
:
/
/
w
w
w
.
l
o
c
.
g
o
v
/
r
r
/
s
c
i
t
e
c
h
/
m
y
s
t
e
r
i
e
s
/
i
m
a
g
e
s
/
L
i
g
h
t
n
i
n
g
_
P
a
r
i
s
_
L
.
j
p
g

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Op amps sense the difference between the inputs and amplifies
that difference, everything is referenced to the circuit ground
We should write
Inverting input=v
1
-ground=v
1
-0
Noninverting input=v
2
-ground=v
2
-0

These voltage differences appear at
the output amplified by the gain A

(v
3
-0)=A[(v
2
-0)-(v
1
-0)]

These zeros just make it confusing, so
leave them off and write:

v
3
=A(v
2
-v
1
)

h
t
t
p
:
/
/
w
w
w
.
l
o
c
.
g
o
v
/
r
r
/
s
c
i
t
e
c
h
/
m
y
s
t
e
r
i
e
s
/
i
m
a
g
e
s
/
L
i
g
h
t
n
i
n
g
_
P
a
r
i
s
_
L
.
j
p
g

Note, the noninverting input and the out put have the same signthey
are in phase, while the inverting input and the output have opposite
sign, they are opposite phase
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.3 Equivalent circuit of the ideal op amp.
Op Amps
Real op amps seem to approach some of the performance of ideal op amps,
but not quite. Ideal characteristics:
Infinite input impedance
Zero output impedance
Zero common-mode gain
(infinite common-mode-
rejection)
Infinite open-loop gain A
Infinite bandwidth
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.3 Equivalent circuit of the ideal op amp.
Op Amps
Real op amps seem to approach some of the performance of ideal op amps,
but not quite. Ideal characteristics:
Infinite input impedance means
The ideal op amp draws no
current from the inputs:
i
1
=i
2
=0
No power drawn from the
inputs
The inputs behave as if they
are open circuits
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.3 Equivalent circuit of the ideal op amp.
Op Amps
Real op amps seem to approach some of the performance of ideal op amps,
but not quite. Ideal characteristics:
Zero output impedance means
The output acts as an ideal
voltage source, able to supply
any amount of current yet
maintain the voltage
The output always supplies
the voltage A(v
2
-v
1
)
The output impedance is zero
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.3 Equivalent circuit of the ideal op amp.
Op Amps
Real op amps seem to approach some of the performance of ideal op amps,
but not quite. Ideal characteristics:
Zero output impedance means
The output acts as an ideal
voltage source, able to supply
any amount of current yet
maintain the voltage
The output always supplies
the voltage A(v
2
-v
1
)
The output impedance is zero
No resistance
herea short
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.3 Equivalent circuit of the ideal op amp.
Op Amps
Real op amps seem to approach some of the performance of ideal op amps,
but not quite. Ideal characteristics:
Zero common-mode gain means
infinite common-mode-rejection
Only the difference is amplified
If v
1
=v
2
the output is 0
If v
1
=v
2
=1.5, the difference is
0, output will be 0, and the
common-mode signal is 1.5
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Real op amps seem to approach some of the performance of ideal op amps,
but not quite. Ideal characteristics:
Zero common-mode gain means
infinite common-mode-rejection
Only the difference is amplified
If v
1
=v
2
the output is 0
If v
1
=v
2
=1.5, the difference is 0,
output will be 0, and the
common-mode signal is 1.5
If v
1
=1.75, v
2
=1.70, then
v
1
-v
2
=(1.75-1.70)=0.05
The difference is 0.05 (this
is amplified)
The common-mode signal
is the average signal,
1.725V (this is rejected)
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Differential and common-mode signals
Differential input signal is the difference
between the inputs

=
2

1

Common-mode input signal is

=
1
2
(
1
+
2
)

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Differential and common-mode signals
Differential input signal is the difference
between the inputs

=
2

1

Common-mode input signal is

=
1
2
(
1
+
2
)

v
Id
and v
Icm
can be used to write the inputs in
a little different and very useful way

1
=

2
=

2


Half the difference between 1 and 2 is added
to the common signal to make input 2
Half the difference between 1 and 2 is
subtracted from the common signal to make
input 1
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Signals on the inputs v
1
and v
2
Common mode and difference signal

=
2

1

=
1
2
(
1
+
2
)
Difference between v
1
and v
2

=
2

1
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Ideally, only the difference signal is amplified, while the common signal is rejected


Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Op Amps
Ideally, only the difference signal is amplified, while the common signal is rejected


Common mode signals are everywherepower supply ripple, instability, noise of
many kinds. Concentrating on the difference signal gives much cleaner results

http://reviseomatic.org/help/2-radio/SignalAndNoise.gif
http://upload.wikimedia.org/wikipe
dia/commons/thumb/5/59/Ru%C3
%ADdo_Noise_041113GFDL.JP
G/800px-
Ru%C3%ADdo_Noise_041113G
FDL.JPG
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.3 Equivalent circuit of the ideal op amp.
Op Amps
Real op amps seem to approach some of the performance of ideal op amps,
but not quite. Ideal characteristics:
Infinite input impedance
Zero output impedance
Zero common-mode gain
(infinite common-mode-
rejection)
Infinite open-loop gain A
Infinite bandwidth
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.3 Equivalent circuit of the ideal op amp.
Op Amps
Real op amps seem to approach some of the performance of ideal op amps,
but not quite. Ideal characteristics:
Infinite open-loop gain A means
Ideally, the open-loop gain is
very large, might as well call it
infinite
Infinite gain is impractical of
course, but open loop gain of real
amplifiers can be very large
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.3 Equivalent circuit of the ideal op amp.
Op Amps
Real op amps seem to approach some of the performance of ideal op amps,
but not quite. Ideal characteristics:
Infinite bandwidth means
The gain does not depend on
frequency
Gain at dc levels is the same as
the gain of a time-varying signal
at any frequency

Of all the ideal specifications,
real op amps may diverge the
most on bandwidth
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.3 Equivalent circuit of the ideal op amp.
Op Amps
Real op amps seem to approach some of the performance of ideal op amps,
but not quite. Ideal characteristics:
Infinite open-loop gain A means
Open-loop is without feedback
(with feedback gain is closed-
loop gain)
The open loop gain of transistors
is not stable in manufacturing
processes, since it is influenced
by properties which naturally
vary, even if slightly
Adding feedback can stabilize the
gain and make amplifier systems
based on transistors much easier
to manufacture. Feedback has
other benefits as well
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Exercise 2.2
a, c; you do b, d
Ideal op amp except gain A=10
3

=
2

1

=
1
2
(
1
+
2
)

1
=

2
=

3
=


v
1
=1.002V, v
2
=0.998V

=
2

1
= 0.998 1.002 = 4

=
1
2

1
+
2
=
1
2
0.998 +1.002 = 1

3
=

= 1000 0.004 = 4
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Exercise 2.2
a, c; you do b, d
Ideal op amp except gain A=10
3

=
2

1

=
1
2
(
1
+
2
)

1
=

2
=

3
=


v
2
=0V, v
3
=2V

=

3

=
2
1000
= 2

=
2

2
= 0
0.002
2
= 1

1
=

2
= 0.001
0.002
2
= 2
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Exercise 2.3
find v
3
and Gain

3
=

=
2

1
=

1
=


2

1

3
=


2

1

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Exercise 2.3
find v
3
and Gain

3
=

=
2

1
=

1
=


2

1

3
=


2

1

= =

=
3
=


2

1

=
2

1

=


2

1
/(
2

1
)
=




Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.5 The inverting closed-loop configuration.
Inverting Configuration
Finally a real op amp

The non-inverting input is at ground
The value of v
1
is referenced to ground at the inverting input

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.5 The inverting closed-loop configuration.
Review -- Inverting Configuration
R
1
and R
2
make a feedback network
The value at the inverting is a result the voltage
divider formed by R
1
and R
2
Information (the voltage, in this case) is fed-back
from the output to the input feedback
R
2
makes a loop, it closes the loop
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
http://ptreport.thrillnetwork.net/images/usf/ripriderockit4.jpg
Figure 2.6 Analysis of the inverting configuration. The circled numbers indicate the order of the analysis steps.
Inverting Configuration
The open-loop gain is A, now define the closed-loop gain as G


Assume the open-loop gain A is very very large
Output is

=
2

1
and A is very large
The larger A is, the closer
2

1
gets to zero, since

approaches zero

2

1
=

= 0
Because of the feedback and the
huge open-loop gain A, the inputs
are forced to be almost the same;
in fact just say the voltage on the
inverting terminal, v
1
should be
nearly zero since

1
=
2
=ground
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.6 Analysis of the inverting configuration. The circled numbers indicate the order of the analysis steps.
2 v
1
=0 (virtual ground)
Inverting Configuration
Because
1
=
2
the two terminals track each other in potential
There is a virtual short circuit between terminals 1 and 2
Since terminal 2 is at ground, terminal 1
is brought to a virtual ground as well
But, terminal 1 and 2 are not shorted
together! The huge open-loop gain of the
amplifier makes it seem as if they are
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.6 Analysis of the inverting configuration. The circled numbers indicate the order of the analysis steps.
2 v
1
=0 (virtual ground)
Inverting Configuration
Now can calculate the current i
1
since
The source voltage v
I
is known
Inverting input voltage v
1
is known (the virtual ground)
Know the voltage on both sides of R
1
, so i
1
is easy to find

1
=

1
=

1
=

1

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.6 Analysis of the inverting configuration. The circled numbers indicate the order of the analysis steps.
2 v
1
=0 (virtual ground)
Inverting Configuration
Since the op amp has ideal infinite input resistance, terminal 1 will not accept the
current, and it all must flow on through R
2
Assume load supplies a lower impedance path to ground

1
=
2
=

1

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.6 Analysis of the inverting configuration. The circled numbers indicate the order of the analysis steps.
2 v
1
=0 (virtual ground)
Inverting Configuration
Since we know the voltage at all nodes, we can calculate the output voltage

=
1

1

2
=
1

2

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.6 Analysis of the inverting configuration. The circled numbers indicate the order of the analysis steps.
2 v
1
=0 (virtual ground)
Inverting Configuration
Since we know the voltage at all nodes, we can calculate the output voltage

=
1

1

2
=
1

2
=

1


And v
O
/v
I
is the closed loop, Gain G
=

1


While the open loop gain A is
infinite, the closed-loop gain is
finite, and controlled by easily
manufactured and controlled passive
resistors.

The uncontrolled gain A is tamed by
negative feedback
0
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Inverting Configuration Effect of Finite Gain
Assume the open-loop gain A is not necessarily large
No longer does

approach zero, instead v


1
is not so close to ground
This changes the current through the feedback resistors
Still assuming infinite input resistance

2

1
=

= (0
1
) =

1
=

1
=

1
=

1

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey

1
=


Inverting Configuration Effect of Finite Gain
As before, all of i
1
goes through R
2
Assume load supplies a lower impedance path to ground
Output voltage=v
1
-drop in R
2

0
=
1

2

2
=

1

2
After some math its possible
to find the closed loop gain

=

2
/
1
1 + 1 +
2
/
1
/

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Inverting Configuration Effect of Finite Gain
As A goes to infinity, G goes to the ideal value =

=

2
/
1
1 + 1 +
2
/
1
/

0
To make the infinite open loop gain approximation, and
have the virtual ground at the inverting input, its not
necessary for A to go to infinity, it just must be large
enough so that the quantity 1 +
2
/
1
/ becomes
very small compared to one.

This happens when 1 +
2
/
1

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
ECE 3210 Fall 2013 John Lindsey
Example 2.1
Calculate closed loop gain for several values of open loop gain for the
inverting configuration with
1
= 1
2
= 100 compare to the ideal
value of g and find the percentage error. Find v
1
when v
I
=0.1V

=

2
/
1
1 + 1 +
2
/
1
/

Substitute these values into the equations for closed loop gain
and try with a variety of values for A with Excel or MATLAB
=


100% =
(
2
/
1
)
(
2
/
1
)
100%

1
=


v
1
is not virtual ground, it is changed by the open loop gain:
Output voltage is related to input voltage by close loop gain:
Substitute in to get a relation for v
1
in terms of v
I
:

1
=


Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc.
ECE 3210 Fall 2013 John Lindsey
Example 2.1
Calculate closed loop gain for several values of open loop gain for the
inverting configuration with
1
= 1
2
= 100 compare to the ideal
value of g and find the percentage error. Find v
1
when v
I
=0.1V
As open lop gain becomes 10,000 and
above, the closed loop gain changes very
little for further changes in open loop gain;
the error becomes small for large A; tiny
changes in v
1
for large changes of large A
A G error v
1

1E+00 0.98 -99% -9.80E-02
1E+01 9.01 -91% -9.01E-02
1E+02 49.75 -50% -4.98E-02
1E+03 90.83 -9.2% -9.08E-03
1E+04 99.00 -1.0% -9.90E-04
1E+05 99.90 -0.10% -9.99E-05
1E+06 99.99 -0.01% -1.00E-05
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc.
Inverting Configuration Input Resistance
Input resistance of the ideal op amp is infinite; for the inverting configuration,
however, the feedback network provides a path from input to ground through the
resistors
Input resistance is defined as


The input current provided by the source is exactly the current flowing through R
1

this makes finding the input resistance simple since already know i
1
from the source
voltage:
This is a problem, actually, since the
closed loop gain G is proportional to
1

1

high input impedance makes for low
gain (or an impractically high R
2
)
Example 2.2 shows one work around
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey

=
1
=

/
1
=
1

Inverting Configuration Output Resistance
Output resistance of the ideal op amp is a shortthe voltage source inside the op
amp can supply any amount of current required by the load to keep the output
voltage steady

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey

=


=

= 0
For the inverting configuration,
the feedback network does not
influence the output resistance
Figure 2.10 A weighted summer.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Weighted Summer
Adds or sums the inputs
Gives a weighta multiplierindividually for each input
Based on the inverting configurationrelies on two concepts
Currents at a node sum, so can add currents
Voltages through resistors in series a multiplied by the resistor divider
The current through any of the
inputs is given by Ohms law


And the currents sum at the
inverting input

=
1
+
2
+ +



Figure 2.10 A weighted summer.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Weighted Summer
The summed current flows through the feedback resistor and the virtual ground at
the inverting input simplifies finding the output voltage

= 0


Substitute in for the summed
currents, and get the output in
terms of the weighted and summed
currents

=
1

+
2

1
+

2
+



The values for R
1
R
n
can be
individually adjusted


Figure 2.10 A weighted summer.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Weighted Summer
Example D2.7

=
1
+5
2
max output 10V current 1mA
Since we are given maximum output currents and voltage, using the virtual
ground R
f
is specified

=
10
0.001
= 10,000
v
2
weighted 5x

1
+

2


Picking a value for R1 then sets a
value for R2

1
+
5

1

2

Or
1

1
=
5

1


if pick R1=10,000
R2=2,000
Figure 2.11 A weighted summer capable of implementing summing coefficients of both signs.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Weighted Summer when some inputs have a different sign
By adding a second op amp, inputs of either sign can be weighted and added
Possible since each stage produces the inverse of the input
Figure 2.12 The noninverting configuration.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Noninverting Configuration
A non-inverting closed-loop amplifier can be made by
Maintaining the feedback network
Moving the source to the non-inverting input
To analyze
Assume ideal op amp with infinite gain
Use the difference equation for the input
Virtual short exists between the inputs

0
= Av
id

= 0 for infinite A
h
t
t
p
:
/
/
u
p
l
o
a
d
.
w
i
k
i
m
e
d
i
a
.
o
r
g
/
w
i
k
i
p
e
d
i
a
/
c
o
m
m
o
n
s
/
t
h
u
m
b
/
1
/
1
e
/
T
o
p
_
T
h
r
i
l
l
_
D
r
a
g
s
t
e
r
_
(
C
e
d
a
r
_
P
o
i
n
t
)
_
0
1
.
j
p
g
/
2
2
0
p
x
-
T
o
p
_
T
h
r
i
l
l
_
D
r
a
g
s
t
e
r
_
(
C
e
d
a
r
_
P
o
i
n
t
)
_
0
1
.
j
p
g

Figure 2.13 Analysis of the noninverting circuit. The sequence of the steps in the analysis is
indicated by the circled numbers.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Noninverting Configuration
Virtual short between the inputs means the source voltage appears at both inputs
Assuming there is an open at the output (and infinite output impedance of the op
amp), the input voltage seen at the inverting input will flow through R1 to ground;
so we can get the current through R1 as

1

The virtual short is not a real short; any current in R1 must come from R2.
Fortunately, the op amp can supply current, since the output is open.

Figure 2.13 Analysis of the noninverting circuit. The sequence of the steps in the analysis is
indicated by the circled numbers.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Noninverting Configuration
Can get the output voltage as the sum of
Voltage drop in R2, which is known since the current is known
Voltage at the noninverting node, which is forced to be the same as the input
voltage by the virtual short (which is due to the huge open-loop gain A)

2

Collect the voltage terms to get closed loop gain:
=

= 1 +

1



Figure 2.12 The noninverting configuration.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Noninverting Configuration with Finite Gain
In the case where A is finite, the closed loop gain can be calculated as

=
1 +

1
1 +
1 +


When A is infinite, the closed loop gain becomes 1 +

1

As with the inverting case,
the bottom of the fraction
becomes close to one when
the A 1 +

1

Its the same result because
the feedback network is the
same (short the sources and
they are identical)
Figure 2.12 The noninverting configuration.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Noninverting Configuration with Finite Gain
Input resistance is infinite
because there are no paths to
ground on the noninverting
terminal
Output resistance is again a
short because of the internal
ideal voltage source
As with the inverting case, the bottom of the fraction becomes close to one
when the A 1 +

1

Its the same result as the inverting configuration because the feedback
network is the same (short the sources and they are identical)

=
1 +

1
1 +
1 +


Figure 2.12 The noninverting configuration.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Noninverting Configuration as a Voltage Follower
To make the noninverting
configuration into a voltage
follower want the closed loop gain
to become 1

The infinite input impedance and zero output impedance make the
noninverting configuration perfect as a voltage follower, also known as a
buffer
A good buffer circuit wont interfere with the source (high input
impedance for a voltage source) and will be able to drive any load (output
impedance a short)
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Noninverting Configuration as a Voltage Follower
This circuit has 100% negative feedback
G1
R1 becomes open
R2 becomes a short

= 1 +

1

0

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Example 2.14
A transducer with an open-circuit voltage of 1V and source resistance of
1M is connected to a 1k load. Find the load voltage for the case of
direction connection and with a unity gain voltage follower

For the direct connection, its a voltage divider

= 1
13
1.0016
=1mV
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Example 2.14
A transducer with an open-circuit voltage of 1V and source resistance of
1M is connected to a 1k load. Find the load voltage for the case of
direction connection and with a unity gain voltage follower

For the voltage follower

= 1
vs
1V
Rs
1mega
RL
1k
follower
1
vo
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers in more detail
Difference amplifies amplify the difference between the two inputs
Rejects all other signals

Real circuits, even reasonable simulations of imaginary circuits will have some
common-mode gain

0
=

= =
2

1

= =
1
2
(
1
+
2
)
A useful figure of merit for real circuits is the common mode rejection ratio
how well a circuit amplifies the difference signal divided by how poorly the
amplifier amplifies the common signal

= 20
|

|
|

|

Figure 2.15 Representing the input signals to a differential amplifier in terms of their
differential and common-mode components.
Difference Amplifiers in more detail
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.16 A difference amplifier.
Difference Amplifiers in more detail
A difference amplifier using feedback to improve stability and performance
Essentially a inverting and noninverting configuration together
The voltage divider of R3 and R4 is used to attenuate the noninverting
signal from 1 +

1
down to the level of the inverting signal

1

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers Analyze by Superposition
Analyzer by superpositionset one input to ground, find the output, then set the
other input to ground, find the output, and add the outputs together
Works because the system is linear
Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers Analyze by Superposition
First ground the noninverting input v
I2
Call the resulting output v
O1
R3 and R4 on the noninvering input have no effect on the circuit output, since
they are at circuit ground on one side, and the infinite impedance input on the
otherno current flows, no voltage exists at input 2
Replacing those with a short to ground then exactly the circuit is the inverting
configuration
Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers Analyze by Superposition
First ground the noninverting input v
I2
Call the resulting output v
O1
R3 and R4 on the noninvering input have no effect on the circuit output, since
they are at circuit ground on one side, and the infinite impedance input on the
otherno current flows, no voltage exists at input 2
Replacing those with a short to ground then exactly the circuit is the inverting
configuration
The gain is:

1
=

1

Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers Analyze by Superposition
Second ground the inverting input v
I1
Call the resulting output v
O2
This is the noninverting configuration, with the voltage divider R3 and R4 on the
input to deal with

2
=

4

3
+
4

2

So the output v
O2
is given by

2
=
2
1 +

1
=
2

4

3
+
4
1 +

1

But we want the gain of the two
inputs to be the same magnitude

Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers Analyze by Superposition
Set the gain portions equal to each other:

2
=
2

4

3
+
4
1 +

1
=
1
=

2

1

Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers Analyze by Superposition
Set the gain portions equal to each other:

2
=
2

4

3
+
4
1 +

1
=
1
=

2

1

Solving only for the gains

3
+
4
1 +

1
=

2

1

Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers Analyze by Superposition
Set the gain portions equal to each other:

2
=
2

4

3
+
4
1 +

1
=
1
=

2

1

Solving only for the gains

3
+
4
1 +

1
=

2

1

Rearrange

3
+
4
=

2

1
1
1 +

1
=

2

1
+
2

Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers Analyze by Superposition
R3 and R4 should be like R2 and R1 to match the gains on the inputs

3
+
4
=

2

1
+
2

3
=

2

1

So back to the output from the non-inverting input

2
=
2
1 +

1
=
2

4

3
+
4
1 +

2
=

2

2

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers Analyze by Superposition
Now finish the superposition by adding the two outputs to find the output

=
2
+
1
=

2

=

2

1

2

1

=

2


This is exactly the form for a difference amplifier, where the gain is

=

2

1

Now must find the common mode gain
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers common mode response
Apply only a common mode signal
Tie the inputs together with V
icm
Then proceed as usual
Find the current in the feedback loop
Find the output voltage
Gain is V
out
/V
Icm

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers common mode response
Find the current in R1
To do that, find the voltage drop across R1
On the left side of R1 there is the common mode voltage


On the right side, there is a virtual short between the two inputs
The feedback network is the thing making the virtual short through the
huge open loop gain Ainput 1 is driven to be a virtual short with
input 2
The voltage on input 2 is from
the R3 R4 divider network

2
=

4

3
+
4


Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers common mode response
The drop in R1 is the difference between the source and input 1

1
=


1
=

1
=
1

3
+
4

1
=

4
+
3
1

1

Now can find the output voltage
Know the drop in R2 due to i
2

Know the voltage at input 1
due to the virtual short
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers common mode response
Find the output voltage

=
1

2

=

4

3
+
4

4
+
3
1

1
R
2

A
cm
=

=

4

3
+
4
1

2
=
1
=

4

3
+
4


1
=
2
=

4
+
3
1

1

Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers common mode response
Find the output voltage
A
cm
=

=

4

3
+
4
1

4


The common mode gain will be zero when

4
= 1
which is the condition established for getting the gain on
both inputs the same:

3
=

2

1

In reality there will be some common
mode gainCMRR will not be infinite
because its impossible to match
resistors perfectly
Figure 2.19 Finding the input resistance of the difference
amplifier for the case R
3
= R
1
and R
4
= R
2
.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Difference Amplifiers input resistance

=
1

+
1


While this difference amplifier can amplify the difference and reject the
common signal, it suffers the low input resistance of the inverting
configurations topology
Find the differential input resistance R
id
given that

3
=

2



The two inputs each have i
I
flowing to their resistors
The virtual short connects the resistors, making a loop

= 2
1

This topology suffers from low input
resistance if high gain is required
Figure 2.20 A popular circuit for an instrumentation
amplifier. (a) Initial approach to the circuit
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Instrumentation Amplifier
Adding a high input impedance amplifier on the input side improves the
low input resistance issue of the difference amplifier
The voltage follower is just the circuit
The voltage follower can have voltage gain if there is some resistance in
the feedback network
Adding some gain before the difference amplifier can be donegive the
difference circuit a larger difference to amplify

A1 and A2 are noninverting with gain
= 1 +

1

Figure 2.20 A popular circuit for an instrumentation
amplifier. (a) Initial approach to the circuit
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Instrumentation Amplifier
The difference signal at the inputs is

=
2

1

Each input is amplified by 1 +

1

At the output of the voltage followers (the input of the difference amplifier A3)

=
2
1 +

1

1
1 +

1
or

(1 +

1
)
The difference amplifier gain is R4/R3 so

=

4

3
1 +
R
2
R
1

Figure 2.20 A popular circuit for an instrumentation
amplifier. (a) Initial approach to the circuit
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Instrumentation Amplifier
However
This configuration will amplify the common mode signal as well as the
differential mode signal
Mismatch between the set of R1/R2 will cause a change in the differential
signal
To change the differential gain, a pair of resistors must be changed instead
of just one resistor
Removing the ground at node X
resolves the issues by relying on the
virtual short circuits between the inputs
created by the infinite open loop gain
Figure 2.20 A popular circuit for an instrumentation
amplifier.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Instrumentation Amplifier
The virtual short between the terminals causes v
I1
and v
I2
to be on either side of
2R
I

The voltage drop in R
I
is then the difference between the inputsjust what
should be amplified
The current in R
I
is then
=

2

1
2


This current then flows through the R2 resistors, producing the voltage at the
input of the difference stage of the amplifier
Figure 2.20 A popular circuit for an instrumentation
amplifier.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Instrumentation Amplifier
Each R2 has a voltage drop of

1

1
=
2
=

R
2

1
=
1

R
2


2

2
=
2
=

2

2
=
2
+

2

The difference between these outputs is the difference amplifiers (A3) input

2

1
=
2
+

2
2

2
2

=
2

1
+

2
2

2
2

2

1
=

1 +
R
2
R
1


Figure 2.20 A popular circuit for an instrumentation
amplifier.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Instrumentation Amplifier
The difference amplifier A3 has a gain of R4/R3, so the overall output is
v
O
= (
2

1
)(
4
/
3
) =

1 +
R
2
R
1
R
4
R
3
and the overall gain is

=
R
4
R
3
1 +
R
2
R
1


Figure 2.20 A popular circuit for an instrumentation
amplifier.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Instrumentation Amplifier
Gains independence from variations in R2 is removedif there are two
different resistors R2: R2 and R2 the differential gain may change, but the
difference signal is preserved since current flows through the resistors in series

=
R
4
R
3
1 +
R
2
+
2

R
1

Overall CMRR of the system is improved since
Common signals at v
I1
and v
I2
will pass through the first stage, but they will
not be amplified
The difference signal is amplified in the first stage
Changing the gain can be done
by adjusting the value of R
I
alone
Figure 2.22 The inverting configuration with general impedances in the feedback and the feed-in paths.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Integrators and Differentiators
Redraw the inverting configuration with impedances instead of resistors
The closed loop transfer function is now

1


Figure 2.24 (a) The Miller or inverting integrator. (b) Frequency
response of the integrator.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Inverting Integrator
Replace resistor R2 with a capacitor
There still is a virtual ground at the inverting input due to the high open loop gain
All of the input voltage drop appears across R, and the current in the
capacitor can then be found

1
=
2
=


After the clock starts at t=o, current through R leaves charge on the plates of
capacitor C, where it accumulates (assuming no leakage) The charge will be:
=
1

0

Figure 2.24 (a) The Miller or inverting integrator. (b) Frequency
response of the integrator.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Inverting Integrator
Recall that V=Q/C, so the voltage accumulating will be, and we should include an
initial condition V
C

=
1

0
+ V
C

And Ohms law relates current and voltage with resistance

=
1

0
+


Figure 2.24 (a) The Miller or inverting integrator. (b) Frequency
response of the integrator.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Inverting Integrator

=
1

0
+


This is the voltage on the input side of the capacitor; the output side is the
opposite sign



So the output is given by the integral:

=
1

0


Figure 2.24 (a) The Miller or inverting integrator. (b) Frequency
response of the integrator.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Inverting Integrator
A different way to analyze starts with the general closed loop transfer function

1


Then substitute in the impedances Z1=R and Z2=1/sC


=
1

=
1
sCR

And =


=
1
CR


Figure 2.24 (a) The Miller or inverting integrator. (b) Frequency
response of the integrator.
Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Inverting Integrator
The circuit has a transfer function magnitude

=
1
CR

And phase of
= +90
As frequency doubles (an octave) magnitude
decreases by half, 20Log0.5=6dB
(20dB/decade)
Where gain becomes 0dB, the frequency is
the integrator frequency, or the inverse of the
time constant

=
1

=
1


Microelectronic Circuits Sedra/Smith Copyright 2010 Oxford University Press, Inc. ECE 3210 Fall 2013 John Lindsey
Inverting Integrator
The circuit has a transfer function magnitude

=
1
CR

At frequency=0, the capacitor passes no signalit
is open. The closed-loop transfer function goes to
infinity, which means the system is now running
without feedbackopen loop gain
dc signals can be amplified greatly by this
circuita problemfix it by adding a
resistor in parallel with the capacitor to allow
some dc feedback gain of R
F
/R
Figure 2.25 The Miller integrator with a large resistance R
F

connected in parallel with C in order to provide negative
feedback and hence finite gain at dc.
V
o
s
V
i
(s)
=
R
F
/R
1 +sCR

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.27 (a) A differentiator. (b) Frequency response of a differentiator with a time-constant CR.
The virtual ground causes the input to appear across the capacitor
Q=VC, and current is Q/time=CV/time
() =

()

= () =


Op Amp Differentiator
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.27 (a) A differentiator. (b) Frequency response of a differentiator with a time-constant CR.
In the frequency domain, the transfer function


=
Op Amp Differentiator
Tend to be unstable
Tend to magnify noise spikes
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.28 Circuit model for an op amp with input offset voltage V
OS
.
Real op amps never perfectly amplify


There is always some extra voltage on v1 or v2, so one or both inputs are slightly
different from the actual input value, and this wrong difference is amplified


2
+


1

Inside the op amp there are transistors, capacitances, resistances, inductances all
with non-ideal values, all with slightly different values for each op amp
manufactured
Offset Voltage
A tiny difference might only
make a V difference, but
many of those can add and
multiplycan easily become a
mV difference
mV still seems small, but
multiply by a large open loop
gain A
d
and its a big factor
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.28 Circuit model for an op amp with input offset voltage V
OS
.
Real op amps never perfectly amplify


There is always some extra voltage on v1 or v2, so one or both inputs are slightly
different from the actual input value, and this wrong difference is amplified


2
+


1

Inside the op amp there are transistors, capacitances, resistances, inductances all
with non-ideal values, all with slightly different values for each op amp
manufactured, and under use also vary
Offset Voltage
A tiny difference might only
make a V difference, but
many of those can add and
multiplycan easily become a
mV difference
mV still seems small, but
multiply by a large open loop
gain A
d
and its a big factor
1mV5mV is typical V
OS
A simple single-input transistor
amplifier
Single input and output
Single power supply 5V


Offset Voltagean example
M2 nchan
Vdd
5V
pchan M3
pchan
M4
Vbias1
2.5
M1
nchan
Ibias
100A
Vin
1.083
Vout
V_in
*0.8 micron model j l with capacitances
.MODEL nchan NMOS LEVEL=3, VT0=0.70 kp=1.265E-4
+ LD=1.2E-7 NSUB=4E15 TOX=1.5E-08 VMAX=2E5
+PHI=0.70 PB=0.65 CJ=8E-5 CJSW=5E-10 MJSW=0.5
+MJ=0.5 CGSO=3.5E-10 CGDO=3.5E-10
*
.MODEL pchan PMOS LEVEL=3 VTO=-0.70 KP=5.75E-5
+LD=1.2E-8 NSUB=3E16 TOX=1.5E-08 VMAX=2E5
+PHI=0.700 PB=0.65 CJ=2E-4 CJSW=1.5E-10 MJSW=0.5
+MJ=0.5 CGSO=3.5E-10 CGDO=3.5E-10
.tf V(Vout) Vin
Cascode Amplifier Homework 5
Sweep input from 0V5V
Output falls from 5V to 0.5V


Offset Voltagean example
Linear region
of operation
A good region to operate might
be with the input centered and
near V
in
=1.083V

Offset Voltagezoom in even more
Change transistor M1 gate width to
12.1 microns from 12.0 microns and
get a very different plotnow need
1.080V V
in
for best operation
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure E2.21 Transfer characteristic of an op amp with V
OS
= 5 mV.
Offset voltages
Caused by slight differences in manufacturing
May be made better or worse through design
Usually are sensitive to use
Temp effects
Voltage supply effects
Wear-out
Offset Voltage
The designer
may expect for
an input=0V, the
output will be 0V
An offset voltage
may cause the
output instead to
rail at 10V
In this case 0V
output occurs
for -5mV input
due to the offset
voltage
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure E2.21 Transfer characteristic of an op amp with V
OS
= 5 mV.
=


Offset Voltage: what is the gain
Question: what
is the gain here
Question: what
is the gain here
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure E2.21 Transfer characteristic of an op amp with V
OS
= 5 mV.
=


Offset Voltage: what is the gain
Is it
10
0
= ?
Is it
0
.005
= 0?

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure E2.21 Transfer characteristic of an op amp with V
OS
= 5 mV.
=


Gain: think about the slope of the transfer characteristic
10 10
0 0.001
= 0
10 0
.006 0.005
=
10
0.001
= +10,000/

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.29 Evaluating the output dc offset voltage due to V
OS
in a closed-loop amplifier.
Offset voltage in the op amp causes the output to be influenced by the
offset voltage just as the non-inverting configurations input

1 +

1

The offsets effect can be removed, in principle, if there is a V
OS
supply
which can be adjusted to the opposite voltage
In a closed-loop
amplifier, the offset
voltage can be
thought of as a shift
in the circuit ground
at the non-inverting
input
Offset Voltage
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.30 The output dc offset voltage of an op amp can be trimmed to zero by connecting a potentiometer to the
two offset-nulling terminals. The wiper of the potentiometer is connected to the negative supply of the op amp.
Commercial Op Amps may have inputs to allow adjustment to remove
the offset voltage
The circuit may still drift due to temperature, supply, age
Offset Voltage Commercial Op Amps Allow Correction
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.31 (a) A capacitively coupled inverting amplifier. (b) The equivalent circuit for determining its dc output offset voltage V
O
.
If the inverting configuration is coupled at the input by a capacitor
Low frequency (and dc) signals are blocked
V
OS
has 100% negative feedback, so passes only at the low level of a
few mVit will be a small error on the amplified AC signal
Offset Voltage DC coupled input
Considering DC input, gain
for V
OS
is 1
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.32 The op-amp input bias currents represented by two current sources I
B1
and I
B2
.
Op Amps have high but non-zero input resistance
Op Amps made from BJTs need some current to runthe bipolar
transistor amplifies a small current in the base
Op Amps made from MOS transistors have very little input current at
low frequencies, but capacitance on the gate allows current to flow at
higher frequencies
Input Bias and Offset Current
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.32 The op-amp input bias currents represented by two current sources I
B1
and I
B2
.
Input Bias and Offset Current
Input bias current is the average of the two input currents

=

1
+
2
2

The input offset current is the difference in the currents

=
1

2

100 Typcially

10 Typically

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.33 Analysis of the closed-loop amplifier, taking into account the input bias currents.
Input Bias and Offset Current Effect
Ground the input signal sources to see the effect of the input currents on the
output voltage
There are currents in R1 and R2, but the non-inverting input is at ground
The virtual short between inputs due to the high open loop gain brings the
inverting input to a virtual short
The output voltage is due to the current in R
2
, I
B1
The current I
B2
has no effect

=
1

2

If R
2
is large, the output will be
significantly affected by the input
bias current
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.34 Reducing the effect of the input bias currents by introducing a resistor R
3
.
Input Bias Current Effect Reduction
Add a resistor R3 to the non-inverting input
Changes the voltage level at the non-inverting input
Through the virtual short between inputs also at the inverting input
The voltage level at the inputs is then:

=
2

3

The current in R1 is defined by the input voltage, since R1 is connected to
ground

1
=

1
=

1

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.34 Reducing the effect of the input bias currents by introducing a resistor R
3
.
Input Bias Current Effect Reduction

1
=

1
=

1

The current in R2 is the sum of the current in R1 and the current supplied by the
input, I
B1

1

2

3

1

This gives the output voltage, which is the drop in R2 and the voltage on the inputs

=
2

3
+
1

2

3

1

2

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.34 Reducing the effect of the input bias currents by introducing a resistor R
3
.
Input Bias Current Effect Reduction
If the bias currents are equal, I
B
=I
B1
=I
B2
then output is simplified to


2

3
(1 +

1

In order to minimize the effects of the bias currents, V
O
should be zero when there
are no input signals as in this case. Minimizing V
O
means adjusting R2 so that
when multiplied by 1 +

1
the result equals R2

3
=

2
1 +

1
=
R
1
R
2
R
1
+ R
2

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.34 Reducing the effect of the input bias currents by introducing a resistor R
3
.
Input Bias Current Effect Reduction
Finally check the value of the offset current in this configuration

1
=

2

2
=

2

Substitute into the output relation

=
2

3
+
1

2

3

1

2

2

This value can be much less
than the effect of the offset
current without the feedback
and R3
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.36 Illustrating the need for a continuous dc path for each of the op-amp input terminals. Specifically, note
that the amplifier will not work without resistor R
3
.
AC coupled amplifier
For AC coupling, there must be a path to ground for the amplifier to work
R3 should be the same as R2
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.37 Determining the effect of the op-amp input offset voltage V
OS
on the Miller integrator circuit.
Note that since the output rises with time, the op amp eventually saturates.
Input offset effect on inverting integrator
For the inverting integrator, input offset current will add linearly to the output,
eventually saturating the outputthe term

increases linearly with time


Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.39 Open-loop gain of a typical general-purpose internally compensated op amp.
Open Loop Gain and Frequency Response
The finite open loop gain of a real Op Amp decreases with frequency above a
certain point
The -3dB frequency f
b
break or corner frequency may be quite low
f
t
is the unity gain frequency, where gain falls to 0db (1V/V)
Gain often falls at -20dB /decade due to internal capacitance making the op
amp a STC circuit
frequency compensation
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.39 Open-loop gain of a typical general-purpose internally compensated op amp.
Open Loop Gain and Frequency Response
For a low-pass STC circuit, gain will be given by
=

1+


Or since s=j
=

1+


A
o
is the dc open loop gain

b
is the -3dB frequency
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.39 Open-loop gain of a typical general-purpose internally compensated op amp.
Open Loop Gain and Frequency Response
For frequencies an order of
magnitude or so beyond the
-3dB frequency, an
approximation for gain is
=


Gain reaches 0dB at
=

=1v/v=0dB



Unity gain bandwidth,
f
t
=
t
/2 is an important
figure of merit given by
manufacturers
Once you know f
t
, you can
work backwards up the
curve to find gain at any
frequency
Gain bandwidth trade-off
The finite-gain closed loop performance of an op amp was found earlier in the
chapter as

1
1 +
1 +


This can be re-written in terms of frequency as

()

()
=

1
1 +
1

(1 +

2
) +

1 +

1

Usually open loop gain is very large, or

1 +

1

Gain bandwidth trade-off
The term in the middle then goes away and closed loop gain then reduces to

()

()
=

1
1 +

1 +

1

This is the form of a low-pass STC where the inverting configuration has
DC gain magnitude is R2/R1
Gain rolls off at -20dB/decade
-3dB point is given by

3
=

1+
2
/
1

Similar math for the non-inverting configuration gives the form of a low-pass
STC where
DC gain magnitude is 1+R2/R1
Gain rolls off at -20dB/decade
-3dB point is given by

3
=

1+
2
/
1


Gain bandwidth trade-off
Example 2.6, find -3dB frequency and gains of closed loop amplifiers
were f
t
=1MHz
The governing rules
are
DC gain
magnitude is
R2/R1
Gain rolls off at -
20dB/decade
-3dB point is
given by

3
=

1 +
2
/
1


Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.42 (a) A noninverting amplifier with a nominal gain of 10 V/V designed using an op amp that saturates at
13-V output voltage and has 20-mA output current limits.
(b) When the input sine wave has a peak of 1.5 V, the output is clipped off at 13 V.
Operating Limits
Op Amps can only reach within about 1V or so of the power supply voltage
For example, if the power supplies are +-5V, output may be maximum of about
+-4V
Current is also limited with similar results
Example where
the amplifier
saturates at +-13V
Operating Limits
Op Amps cant respond quickly enough in a second way, different from frequency
response
A large load requires a large current, for instance charging a large capacitance.
If the current required is large enough, the output voltage will lag a change in
the input voltage
The maximum rate of change is the Slew Rate
=


Typically specified as volts/microsecond=V/s
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Operating Limits
Slew rate limitedwhile an amplifier is slewing the output voltage
rises at a fixed rate
Result is a non-linear distortion in the output
Sharply rising input
Slew-rate exceeded, the
output rises at the SR
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.44 Effect of slew-rate limiting on output sinusoidal waveforms.
Operating Limits
Slew rate limitedwhile an
amplifier is slewing the output
voltage rises at a fixed rate
Result is a non-linear distortion in
the output

S-ar putea să vă placă și