VLSI Technology and Applications

Contents
MOS Memory-RAM
Static RAM
Dynamic RAM
ROM
Sense Amplifier
Address Decoder

Introduction
Storage of large information.

Low Power Memory requirement.

Advanced fabrication technologies and compact design.

On chip memories in VLSI.
4
Classification of Semiconductor Memory
Based on R/W
Operation
RAM (Volatile)
ROM (Non-
volatile)
Based on Fabrication

Memory using Bipolar transistor
Memory using unipolar transistor
(MOS)
Equivalent Circuits of Memory Cells
a) DRAM, b) SRAM, c) Mask (Fuse) ROM, d) EPROM, e) FRAM
Memory Organization
Memory organization Example Contd
Cell stored in core:
2
n
x 2
m

n = m = 8,

Total no. of cells = 65536

Peripheral circuits:

Decoder,
Sense amplifier
Column precharge
Data buffer.
DRAM Cell Design
The four-transistor DRAM cell.

For write: WL enabled & complement data written from bit lines.

Data stored as charge at parasitic & gate capacitors.

For read: Voltage of bit line discharged.
Three-Transistor DRAM Cell
M
1
write & M
2
read switches, M
3
storage device.

Write operation: WL enable, voltage of write bit line passed
to storage device through M
1
.

Read operation: Voltage of bit line discharged.
M
1
M
2
M
3
Two transistor DRAM cell
For write: Wbl driven with data, then raise wl (write line) allow
data to store node.

For read: precharge rbl & allow read transistor to turn on by
pulling rl low.

Logic 1: pull rbl low, Logic 0: rbl unchanged.

V
rbl
compared with V
ref
to complete readout.
One-transistor DRAM cell
Industry standard DRAM.

Separate capacitor for each storage cell.

Write operation: WL enable, data stored at C through
transistor.

Read operation: destructive.
DRAM cell Capacitor
a) DRAM cell with cylindrical stacked capacitor
b) DRAM cell with a trench capacitor.


SRAM cell
Storage: Cross coupled inverters

Full CMOS SRAM cell
SRAM Cell Design
Basic SRAM Cell

Two cross coupled invertors
and access transistor.

WL: Select line, BL R/W line.

WL=0: Hold state,
WL=1 R/W operation.
Voltage Transfer Characteristics

Store valve at two stable states

Cell state change with V
th
.

SNM: Separation in two curve.
Six Transistor (6T) SRAM
Read Operation

& pre-charged to high.

When WL high: current flow
M
3
& M
1
to ground.

Current discharge C
bit
.

Diff. b/w & sensed.
Read operation waveform

V: voltage diff. b/w & .

Target delay.

Problem: Current through M
3
& M
1

rise voltage at q.
b b
b
b b
b
Six Transistor (6T) SRAM Contd
Write Operation

To write 1, forced
to low.

To write 0 forced
to low.

Write 1 operation.
Voltage Transfer Characteristics

Pull low before WL high.

Regeneration action when WL high.
b
b
b
Four Transistor (4T) SRAM
Large R, lower current & high power consumption. Large
R noisy.

Adv: Small area, High packing density.

Disadv: Extra processing steps, high power consumption,
lower SNM.
Leakage Currents in SRAM
Sub-threshold leakage current
Gate tunneling current

Leakage Currents in SRAM Cell
1. Subthreshold Current
The drain-source current of a transistor
when the gate-source voltage is less
than the threshold voltage.


Equation suggests two ways to reduce
I
sub
-
Turn off supply voltage (V=0)
Increase threshold voltage

The problem with the first approach is
loss of state; with the second approach
is the loss of performance!



Leakage in SRAM Cell
2. Gate Tunneling Leakage
Electrons (holes) tunneling from
the bulk silicon through the gate
oxide into the gate results in gate
tunneling current in an NMOS
(PMOS) transistor





Increasing T
ox
reduces gate
leakage but degrades transistors
effectiveness as T
ox
must decrease
proportionally with process scaling
to avoid short channel effects.

Static Noise Margin (SNM)

SNM quantifies the amount of voltage noise required at the internal
nodes of a bitcell to flip the cells content.

Degraded SNM limits voltage scaling for SRAM designs.

Static Noise Margin (SNM) (contd )





Inverter 2 Inverter 1
WL
BLB
BL
Q QB
M1
M2
M3
M4
M5
M6
V
N
V
N To obtain it, the voltage at Q is plotted
against QB for the sweep from left to right
and then right to left
SNM is length of side of the
largest embedded square
on the butterfly curve
Low Power SRAM Design
Low power circuit technique: Memory cell, sense amplifier &
precharging circuit.

Applications: Laptop, notebook, IC memory cards.

Power Dissipation in SRAM

Active power dissipation:

Decoder, memory cell, I/O ckt & write ckt.
P
mem-array
= mP
act
+ (n - l) m P
leak
+ m I
dc
t f V
DD.
Reduce WL capacitance, DC current, supply voltage.

Standby Power Dissipation

P
standby
= m n P
leak
Reduce supply voltage, leakage current increase due to V
th

reduction.
Low Power Techniques
Banked Organization of SRAM

Reduce switching speed.
n = R x C, Total switching capacitance = R x C x C
cell

Splitting memory reduce switching capacitance.

(R x C x C
cell
)/B
Low Power Techniques Contd
Divided world line architecture

WL delay reduced by dividing WL in parts.

Global WL & Local WLs.

DWL technique for high density, high speed & low power.
Low Power Techniques Contd
Hierarchical Word Decoding (HWD)

For SRAM more then 4Mb, no. of blocks increased In DWL.

Capacitance of global WL increases, delay & power increase.

Word select line divided into more levels.
Low Power Techniques Contd
Bit-Line Capacitance Reduction
Reducing no. of cells per bit line by multidivided bit line
technique.

Low Power Techniques Contd
Pulse Generator

Enable WL for time need to bit cell discharge.

WL & sense amplifier controlled by delay.


Read-Only Memory Cells
WL
BL
WL
BL
1
WL
BL
WL
BL
WL
BL
0
V
DD
WL
BL
GND
Diode ROM MOS ROM 1 MOS ROM 2
Diode ROM: Presence or absence of diode represent 1 or 0
MOS ROM: Diode replaced with gate-source connection of an nMOS
Disadv: Additional power supply line required.
Different approaches to implement 1 and 0 ROM cell
MOS ROM
WL [0]
V
DD
BL [0]
WL [1]
WL [2]
WL [3]
V
bias
BL [1]
Pull-down loads
BL [2] BL [3]
V
DD
4x4 Array: Overhead of supply lines reduced by sharing b/w cells. This
requires the mirroring of the odd cells around the horizontal axis.
Non-Volatile Memories
The Floating-gate Avalanche-injection transistor (FAMOS)
Floating gate
Source
Substrate
Gate
Drain
n
+
n
+_
p
t
ox
t
ox
Device cross-section
Schematic symbol
G
S
D
An extra polysilicon strip is inserted b/w gate and channel.
Double the oxide thickness, V
th
increased.
High V
ds
create high electric field and causes avalanche injection.
Hot electron effect.

Floating-Gate Transistor Programming
20 V
10 V 5 V
20 V
D S
Avalanche injection
A Programmable-Threshold Transistor
FLOTOX EEPROM
Floating-gate Tunneling Oxide
Floating gate
Source
Substrate
p
Gate
Drain
n
1
n
1
FLOTOX transistor
Fowler-Nordheim
I-V characteristic
20 30 nm
10 nm
-10 V
10 V
I
V
GD
EEPROM Cell
WL
BL
V
DD
Absolute threshold control
is hard
Unprogrammed transistor
might be depletion
2 transistor cell
Flash EEPROM
Control gate
erasure
p- substrate
Floating gate
Thin tunneling oxide
n
1
source
n
1
drain
programming
Many other options
Basic Operations in a NOR Flash Memory
Erase
Basic Operations in a NOR Flash Memory
Write
Basic Operations in a NOR Flash Memory
Read
Memory Architecture: Decoders
Word 0
Word 1
Word 2
Word N
2
2
Word N
2
1
Storage
cell
M bits M bits
N
words
S
0
S
1
S
2
S
N
2
2
A
0
A
1
A
K
2
1
K
5
log
2
N
S
N
2
1
Word 0
Word 1
Word 2
Word N
2
2
Word N
2
1
Storage
cell
S
0
Input-Output
( M bits)
Intuitive architecture for N x M memory
Too many select signals:
N words == N select signals
K = log
2
N
Decoder reduces the number of select signals
Input-Output
( M bits)
Decoder
Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
Row Decoders
Collection of 2
M
complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
Hierarchical Decoders


A
2
A
2
A
2
A
3
WL
0
A
2
A
3
A
2
A
3
A
2
A
3
A
3
A
3
A
0
A
0
A
0
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
1
A
1
WL
1
Multi-stage implementation improves performance
NAND decoder using
2-input pre-decoders
Dynamic Decoders
Precharge devices
V
DD
f
GND
WL
3
WL
2
WL
1
WL
0
A
0
A
0
GND
A
1
A
1
f
WL
3
A
0
A
0
A
1
A
1
WL
2
WL
1
WL
0
V
DD
V
DD
V
DD
V
DD
2-input NOR decoder 2-input NAND decoder
4-input pass-transistor based column decoder
Advantages: speed (t
pd
does not add to overall memory access time)
Only one extra transistor in signal path
Disadvantage: Large transistor count


2-input NOR decoder
A
0
S
0
BL
0
BL
1
BL
2
BL
3
A
1
S
1
S
2
S
3
D
4-to-1 tree based column decoder
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
buffers
progressive sizing
combination of tree and pass transistor approaches
Solutions:
BL
0
BL
1
BL
2
BL
3
D
A
0
A
0
A
1
A
1
Decoder for circular shift-register
V
DD
V
DD
R
WL
0
V
DD
f
f
f
f
V
DD
R
WL
1
V
DD
f
f
f
f
V
DD
R
WL
2
V
DD
f
f
f
f

Sense Amp Operation
D V (1)
V (1)
V (0)
t
V
PRE
V
BL
Sense amp activated
Word line activated
Sense Amplifiers
t
p
C
D
V

I
av
---------------- =
make
D
V as small
as possible
small large
Idea: Use Sense Amplifer
output input
s.a.
small
transition
Differential Sense Amplifier
Directly applicable to
SRAMs
M
4
M
1
M
5
M
3
M
2
V
DD
bit bit
SE
Out
y
Differential Sensing SRAM
V
DD
V
DD
V
DD
V
DD
BL
EQ
Diff.
Sense
Amp
(a) SRAM sensing scheme (b) two stage differential amplifier
SRAM cell i
WL
i
2
x x
V
DD
Output
BL
PC
M
3
M
1
M
5
M
2
M
4
x
SE
SE
SE
Output
SE
x
2
x
2
x
y
y
2
y
Latch-Based Sense Amplifier (DRAM)
Initialized in its meta-stable point with EQ
Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
EQ
V
DD
BL BL
SE
SE